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LTC2348-16 Datasheet(PDF) 34 Page - Linear Technology

Part No. LTC2348-16
Description  Octal, 16-Bit, 200ksps Differential ±10.24V Input SoftSpan ADC with Wide Input Common Mode Range
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Maker  LINER [Linear Technology]
Homepage  http://www.linear.com
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LTC2348-16 Datasheet(HTML) 34 Page - Linear Technology

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LTC2348-16
34
234816fa
For more information www.linear.com/LTC2348-16
Typically, applications will update the SoftSpan configura-
tion register in the manner shown in Figures 17 and 18.
After the opening of a new data transaction window at the
falling edge of BUSY, the user supplies a 24-bit SoftSpan
configuration word on SDI during the first 24 SCKI cycles.
Thisnewwordoverwritestheinternalconfigurationregister
contentsfollowingthe24thSCKIrisingedge. Theuserthen
holds SDI low for the remainder of the data transaction
windowcausingtheregistertoretainitscontentsregardless
of the number of additional SCKI cycles applied. SoftSpan
settings may be retained across multiple conversions by
holding SDI low for the entire data transaction window,
regardless of the number of SCKI cycles applied.
Serial LVDS I/O Mode
In LVDS I/O mode, information is transmitted using posi-
tive and negative signal pairs (LVDS+/LVDS) with bits
differentially encoded as (LVDS+ − LVDS). These signals
are typically routed using differential transmission lines
with 100Ω characteristic impedance. Logical 1’s and 0’s
are nominally represented by differential +350mV and
−350mV,respectively.Forclarity,allLVDStimingdiagrams
and interface discussions adopt the logical rather than
physical convention.
As shown in Figure 20, in LVDS I/O mode the serial data
bus consists of a serial clock differential input, SCKI, serial
data differential input, SDI, serial clock differential output,
SCKO, and serial data differential output, SDO. Communi-
cation with the LTC2348-16 across this bus occurs during
predefined data transaction windows. Within a window,
the device accepts 24-bit SoftSpan configuration words
for the next conversion on SDI and outputs 24-bit packets
containing conversion results and channel configuration
information from the previous conversion on SDO. New
data transaction windows open 10ms after powering up
or resetting the LTC2348-16, and at the end of each con-
version on the falling edge of BUSY. In the recommended
use case, the data transaction should be completed with
a minimum tQUIET time of 20ns prior to the start of the
next conversion, as shown in Figure 20. New SoftSpan
configuration words are only accepted within this recom-
mended data transaction window, but SoftSpan changes
S23
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5
S3
S4
S1
S2
S0
DON’T CARE
SCKI
SDI
SoftSpan CONFIGURATION WORD
CMOS I/O MODE
SoftSpan CONFIGURATION WORD
INTERNAL 24-BIT SoftSpan CONFIGURATION REGISTER
(SAME FOR CMOS AND LVDS)
LVDS I/O MODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
tSCKI
S23
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5
S3
S4
S1
S2
S0
DON’T CARE
SCKI
(LVDS)
SDI
(LVDS)
tSCKI
CHANNEL 7 SoftSpan
CODE SS[2:0]
CHANNEL 6 SoftSpan
CODE SS[2:0]
CHANNEL 5 SoftSpan
CODE SS[2:0]
CHANNEL 4 SoftSpan
CODE SS[2:0]
CHANNEL 3 SoftSpan
CODE SS[2:0]
CHANNEL 2 SoftSpan
CODE SS[2:0]
CHANNEL 1 SoftSpan
CODE SS[2:0]
CHANNEL 0 SoftSpan
CODE SS[2:0]
234816 F19
tSCKIH
tSCKIL
tSSDISCKI
tHSDISCKI
tSCKIH
tSCKIL
tHSDISCKI
tHSDISCKI
tSSDISCKI
tSSDISCKI
Figure 19. Mapping Between Serial SoftSpan Configuration Word, Internal SoftSpan
Configuration Register, and SoftSpan Code for Each Analog Input Channel
applicaTions inForMaTion


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