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LTC2348-16 Datasheet(PDF) 19 Page - Linear Technology

Part No. LTC2348-16
Description  Octal, 16-Bit, 200ksps Differential ±10.24V Input SoftSpan ADC with Wide Input Common Mode Range
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Maker  LINER [Linear Technology]
Homepage  http://www.linear.com

LTC2348-16 Datasheet(HTML) 19 Page - Linear Technology

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applicaTions inForMaTion
The LTC2348-16 is a 16-bit, low noise 8-channel simulta-
neous sampling successive approximation register (SAR)
ADC with differential, wide common mode range inputs.
The ADC operates from a 5V low voltage supply and
flexible high voltage supplies, nominally ±15V. Using the
integratedlow-driftreferenceandbuffer(VREFBUF = 4.096V
nominal), each channel of this SoftSpan ADC can be in-
dependently configured on a conversion-by-conversion
basis to accept ±10.24V, 0V to 10.24V, ±5.12V, or 0V to
5.12V signals. The input signal range may be expanded
up to ±12.5V using an external 5V reference. Individual
channels may also be disabled to increase throughput on
the remaining channels.
The wide input common mode range and high CMRR
(118dB typical, VIN+ = VIN– = 18VP-P 200Hz Sine) of the
a variety of signals, simplifying signal chain design. The
absolute common mode input range is determined by
the choice of high voltage supplies, which may be biased
asymmetrically around ground and include the ability for
either the positive or negative supply to be tied directly to
ground. This input signal flexibility, combined with ±1LSB
INL, no missing codes at 16-bits, and 94.4dB SNR, makes
the LTC2348-16 an ideal choice for many high voltage
applications requiring wide dynamic range.
The LTC2348-16 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces, enabling it to com-
municate equally well with legacy microcontrollers and
modern FPGAs. In CMOS mode, applications may employ
between one and eight lanes of serial output data, allowing
the user to optimize bus width and data throughput. The
LTC2348-16 typically dissipates 140mW when converting
channel throughput. Optional nap and power down modes
may be employed to further reduce power consumption
during inactive periods.
The LTC2348-16 operates in two phases. During the ac-
quisition phase, the sampling capacitors in each channel’s
sample-and-hold (S/H) circuit connect to their respective
analog input pins and track the differential analog input
voltage (VIN+ – VIN–). A rising edge on the CNV pin transi-
tions all channels’ S/H circuits from track mode to hold
mode, simultaneously sampling the input signals on all
phase, each channel’s sampling capacitors are connected,
one channel at a time, to a 16-bit charge redistribution
capacitor D/A converter (CDAC). The CDAC is sequenced
fractions of the channel’s SoftSpan full-scale range
(e.g., VFSR/2, VFSR/4 … VFSR/65536) using a differential
comparator. At the end of this process, the CDAC output
approximates the channel’s sampled analog input. Once
all channels have been converted in this manner, the ADC
control logic prepares the 16-bit digital output codes from
each channel for serial transfer.
range into 216 levels. In conjunction with the ADC master
reference voltage, VREFBUF, a channel’s SoftSpan configu-
ration determines its input voltage range, full-scale range,
LSB size, and the binary format of its conversion result, as
shown in Tables 1a and 1b. For example, employing the
internal reference and buffer (VREFBUF = 4.096V nominal),
SoftSpan 7 configures a channel to accept a ±10.24V bi-
polar analog input voltage range, which corresponds to a
convert both larger and smaller bipolar and unipolar input
ranges. Conversion results are output in two’s comple-
ment binary format for all bipolar SoftSpan ranges, and
in straight binary format for all unipolar SoftSpan ranges.
The ideal two’s complement transfer function is shown in
Figure 2, while the ideal straight binary transfer function
is shown in Figure 3.

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