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LTC6652 Datasheet(PDF) 6 Page - Linear Technology |
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LTC6652 Datasheet(HTML) 6 Page - Linear Technology |
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6 / 32 page  LTC2320-12 6 Rev B For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground, or above VDD or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground, or above VDD or OVDD, without latch-up. Note 4: VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 = 4.096V, fSMPL = 1.5MHz. Note 5: Recommended operating conditions. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 0 and 1111 1111 1111 1. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Note 8: All specifications in dB are referred to a full-scale ±4.096V input with REF = 4.096V. Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer must be turned off by setting REFBUFEN = 0V. Note 10: fSMPL = 1.5MHz, IREFOUT1,2,3,4 varies proportionally with sample rate. Note 11: Guaranteed by design, not subject to test. Note 12: Parameter tested and guaranteed at OVDD = 1.71V and OVDD = 2.5V. Note 13: tSCK of 9.1ns allows a shift clock frequency up to 105MHz for rising edge capture. Note 14: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 15: CNV is driven from a low jitter digital source, typically at OVDD logic levels. ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns CMOS I/O Mode, DDR CMOS/LVDS = GND, SDR/ DDR = OVDD tSCK SCK Period l 18.2 ns tSCKH SCK High Time l 8.2 ns tSCKL SCK Low Time l 8.2 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4.5 ns tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns LVDS I/O Mode, SDR CMOS/LVDS = OVDD, SDR/DDR = GND tSCK SCK Period l 3.3 ns tSCKH SCK High Time l 1.5 ns tSCKL SCK Low Time l 1.5 ns tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF OVDD = 2.5V l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay OVDD = 2.5V l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns LVDS I/O Mode, DDR CMOS/LVDS = OVDD, SDR/DDR = OVDD tSCK SCK Period l 6.6 ns tSCKH SCK High Time l 3 ns tSCKL SCK Low Time l 3 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF OVDD = 2.5V l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay OVDD = 2.5V l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns |
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