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LTC2312-14 Datasheet(PDF) 8 Page - Linear Technology |
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LTC2312-14 Datasheet(HTML) 8 Page - Linear Technology |
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8 / 22 page  LTC2312-14 8 231214fa For more information www.linear.com/LTC2312-14 TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 500ksps, unless otherwise noted. PIN FUNCTIONS VDD (Pin 1): Power Supply. The ranges of VDD are 2.7V to 3.6V and 4.75V to 5.25V. Bypass VDD to GND with a 2.2µF ceramic chip capacitor. REF (Pin 2): Reference Input/Output. The REF pin volt- age defines the input span of the ADC, 0V to VREF. By default, REF is an output pin and produces a reference voltage VREF of either 2.048V or 4.096V depending on VDD (see Table 2). Bypass to GND with a 2.2µF, low ESR, high quality ceramic chip capacitor. The REF pin may be overdriven with a voltage at least 50mV higher than the internal reference voltage output. GND (Pin 3): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 4): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VREF. OVDD (Pin 5): I/O Interface Digital Power. The OVDD range is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V or 5V). Bypass to GND with a 2.2µF ceramic chip capacitor. SDO (Pin 6): Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with the MSB first through the LSB last. The data stream consists of 14 bits of conversion data followed by trailing zeros. There is no cycle latency. Logic levels are determined by OVDD. SCK (Pin 7): Serial Data Clock Input. The SCK serial clock synchronizes the serial data transfer. SDO data transitions on the falling edge of SCK. Logic levels are determined by OVDD. CONV (Pin 8): Convert Input. This active high signal starts a conversion on the rising edge. The conversion is timed via an internal oscillator. The device automatically powers down following the conversion process. The SDO pin is in high impedance when CONV is a logic high. Bringing CONV low enables the SDO pin and outputs the MSB. Subsequent bits of the conversion data are read out seri- ally on the falling edge of SCK. A logic low on CONV also placesthesample-and-holdintosamplemode.Logiclevels are determined by OVDD. Output Supply Current (IOVDD) vs Output Supply Voltage (OVDD) Supply Current (IVDD) vs Supply Voltage (VDD) TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT SUPPLY VOLTAGE (V) 1.8 0 0.1 0.2 0.5 0.4 0.3 2.6 2.2 3.4 3.0 3.8 4.2 4.6 5.0 231214 G19 SUPPLY VOLTAGE (V) 2.6 2.50 2.75 3.00 3.25 3.50 2.9 3.8 3.5 3.2 4.1 4.7 4.4 5.3 5.0 231214 G18 OPERATION NOT ALLOWED |
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Similar Description - LTC2312-14 |
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