Page 24 of 27

256Mb F-die DDR2 SDRAM

Rev. 1.5 Feb. 2005

DDR2 SDRAM

For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the

datasheet tIS(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively. Example:

tIS (total setup time) = tIS(base) + delta tIS

19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for

this parameter, but system performance (bus turnaround) will degrade accordingly.

20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as pro-

vided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For

example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock source, and

less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.

21. tQH = tHP – tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).

tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the

next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-

channel to n-channel variation of the output drivers.

22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the

output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given

cycle.

23. DAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up.

WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an inte-

ger, round up to the next highest integer. tCK refers to the application clock period.

Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks.

tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

24. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In

case of clock frequency change during precharge power-down, a specific procedure is required as described

in DDR2 device operation

25. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

26. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

27. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are ref-

erenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins

driving (tLZ). Following figure shows a method to calculate the point when device is no longer driving (tHZ), or

begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points

are not critical as long as the calculation is consistent.

28. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when

the device output is no longer driving (tRPST), or begins driving (tRPRE). Following figure shows a method to

calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring

the signal at two different voltages. The actual voltage measurement points are not critical as long as the cal-