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IDT72V261LA Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT72V261LA Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 27 page COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 6 Commercial Com’l & Ind’l(2) Commercial IDT72V261LA10 IDT72V261LA15 IDT72V261LA20 IDT72V271LA10 IDT72V271LA15 IDT72V271LA20 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit fS Clock Cycle Frequency — 100 — 66.7 — 50 MHz tA Data Access Time 2 6.5 2 10 2 12 ns tCLK Clock Cycle Time 10 — 15 — 20 — ns tCLKH Clock High Time 4.5 — 6 — 8 — ns tCLKL Clock Low Time 4.5 — 6 — 8 — ns tDS Data Setup Time 3 — 4 — 5 — ns tDH Data Hold Time 0.5 — 1 — 1 — ns tENS Enable Setup Time 3 — 4 — 5 — ns tENH Enable Hold Time 0.5 — 1 — 1 — ns tLDS Load Setup Time 3 — 4 — 5 — ns tLDH Load Hold Time 0.5 — 1 — 1 — ns tRS Reset Pulse Width(3) 10 — 15 — 20 — ns tRSS Reset Setup Time 10 — 15 — 20 — ns tRSR Reset Recovery Time 10 — 15 — 20 — ns tRSF Reset to Flag and Output Time — 10 — 15 — 20 ns tFWFT Mode Select Time 0 — 0 — 0 — ns tRTS Retransmit Setup Time 3 — 4 — 5 — ns tOLZ Output Enable to Output in Low Z(4) 0— 0—0 — ns tOE Output Enable to Output Valid 2 6 3 8 3 10 ns tOHZ Output Enable to Output in High Z(4) 26 38 3 10 ns tWFF Write Clock to FF or IR — 6.5 — 10 — 12 ns tREF Read Clock to EF or OR — 6.5 — 10 — 12 ns tPAF Write Clock to PAF — 6.5 — 10 — 12 ns tPAE Read Clock to PAE — 6.5 — 10 — 12 ns tHF Clock to HF —16 — 20 — 22 ns tSKEW1 Skew time between RCLK and WCLK for 5 — 6 — 10 — ns FF/IR tSKEW2 Skew time between RCLK and WCLK for 12 — 15 — 20 — ns PAE and PAF tSKEW3 Skew time between RCLK and WCLK for 60 — 60 — 60 — ns EF/OR AC ELECTRICAL CHARACTERISTICS(1) (Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C) NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for 15ns speed grade is available as a standard device. All other speed grades are available by special order. 3. Pulse widths less than minimum values are not allowed. 4. Values guaranteed by design, not currently tested. Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 1 AC TEST CONDITIONS * Includes jig and scope capacitances. 4673 drw 04 330 Ω 30pF* 510 Ω 3.3V D.U.T. Figure 2. Output Load |
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