HFA3863 datasheet(4/39 Pages) INTERSIL

Part #	HFA3863

Description	Direct Sequence Spread Spectrum Baseband Processor

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Manufacturer	INTERSIL [Intersil Corporation]

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4-4

External Interfaces

There are three primary digital interface ports for the

HFA3863 that are used for conﬁguration and during normal

operation of the device as shown in Figure 1. These ports

are:

• The Control Port, which is used to conﬁgure, write

and/or read the status of the internal HFA3863

registers.

• The TX Port, which is used to accept the data that

needs to be transmitted from the network processor.

• The RX Port, which is used to output the received

demodulated data to the network processor.

In addition to these primary digital interfaces the device

includes a byte wide parallel Test Port which can be

conﬁgured to output various internal signals and/or data.

The device can also be set into various power consumption

modes by external control. The HFA3863 contains three

Analog to Digital (A/D) converters and four Digital to Analog

converters. The analog interfaces to the HFA3863 include,

the In phase (I) and quadrature (Q) data component inputs/

outputs, and the RF and IF receive automatic gain control

and transmit output power control.

MD_RDY

54

O

MD_RDY is an output signal to the network processor, indicating header data and a data packet are

ready to be transferred to the processor. MD_RDY is an active high signal that signals the start of data

transfer over the RXD serial bus. MD_RDY goes active when the SFD (Note) is detected and returns

to its inactive state when RX_PE goes inactive or an error is detected in the header.

RX_PE

61

I

When active, the receiver is conﬁgured to be operational, otherwise the receiver is in standby mode.

This is an active high input signal. In standby, RX_PE inactive, all RX A/D converters are disabled.

SD

3

I/O

SD is a serial bidirectional data bus which is used to transfer address and data to/from the internal

registers. The bit ordering of an 8-bit word is MSB ﬁrst. The ﬁrst 8 bits during transfers indicate the

register address immediately followed by 8 more bits representing the data that needs to be written or

read at that register. In the 4 wire interface mode, this pin is three-stated unless the R/W pin is high.

SCLK

4

I

SCLK is the clock for the SD serial bus. The data on SD is clocked at the rising edge. SCLK is an input

clock and it is asynchronous to the internal master clock (MCLK). The maximum rate of this clock is

11MHz or one half the master clock frequency, whichever is lower.

SDI

64

I

Serial Data Input in 3 wire mode described in Tech Brief 383. This pin is not used in the 4 wire interface

described in this data sheet. It should not be left ﬂoating.

R/W5

I

R/W is an input to the HFA3863 used to change the direction of the SD bus when reading or writing

data on the SD bus. R/W must be set up prior to the rising edge of SCLK. A high level indicates read

while a low level is a write.

CS

6

I

CS is a Chip select for the device to activate the serial control port. The CS doesn’t impact any of the

other interface ports and signals, i.e., the TX or RX ports and interface signals. This is an active low

signal. When inactive SD, SCLK, and R/W become “don’t care” signals.

TEST 7:0

51, 50, 49,

48, 47, 46,

45, 44

I/O

This is a data port that can be programmed to bring out internal signals or data for monitoring. These

bits are primarily reserved by the manufacturer for testing. A further description of the test port is given

in the appropriate section of this data sheet.

RESET

63

I

Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the

HFA3863 goes into the power standby mode. RESET does not alter any of the conﬁguration register

values nor does it preset any of the registers into default values. Device requires programming upon

power-up. See the section on Control Register 2 bit 0 for important initialization information.

MCLK

42

I

Master Clock for device. The nominal frequency of this clock is 44MHz. This is used internally to

generate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks.

TXI

±

23/24

O

TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/24-.

TXQ

±

29/30

O

TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential

29+/30-.

CompCap

33

I

Compensation Capacitor.

CompCap2

26

I

Compensation Capacitor.

CompRes1

32

I

Compensation Resistor.

CompRes2

27

I

Compensation Resistor.

NOTE: See CR10[3].

Pin Descriptions (Continued)

NAME

TYPE I/O

DESCRIPTION

HFA3863

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