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ESDA6V1-4F1 Datasheet(PDF) 4 Page - STMicroelectronics

Part No. ESDA6V1-4F1
Description  QUAD TRANSIL ARRAY FOR ESD PROTECTION
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ESDA6V1-4F1 Datasheet(HTML) 4 Page - STMicroelectronics

   
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ESDA6V1-4F1
As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs
rectangular surge is well adapted. In addition both rise and fall times are optimised to avoid any parasitic
phenomenon during the measurement of Rd.
The ESDA6V1-4F1 has been designed to clamp fast spikes like ESD. Generally the PCB designers need
to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the
classical parameters.
The voltage across the protection cell can be calculated with the following formula:
VV
R
I
CL
BR
d
PP
=+
Where IPP is the peak current through the ESDA cell.
USE OF THE DYNAMIC RESISTANCE
CALCULATION OF THE CLAMPING VOLTAGE
The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the
classical 8/20 µs and 10/1000 µs surges
DYNAMIC RESISTANCE MEASUREMENT
t
t
I
IPP
2µs
2.5 µs
2.5 µs duration measurement wave
With the focus of lowering the operation levels, the problem of malfunction caused by the environment is
critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system.
Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in
suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such
that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice
for minimal lead inductance. They serve as parallel protection elements, connected between the signal line
to ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low
impedance path diverting the transient current to ground.
ESD PROTECTION WITH ESDA6V1-4F1


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