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DS21554 Datasheet(PDF) 1 Page - Maxim Integrated Products |
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DS21554 Datasheet(HTML) 1 Page - Maxim Integrated Products |
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1 / 124 page  1 of 124 REV: 021004 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS21354/DS213554 single-chip transceivers (SCTs) contain all the necessary functions to connect to E1 lines. The devices are upward-compatible versions of the DS2153 and DS2154 SCTs. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. Both devices automatically adjust to E1 22AWG (0.6mm) twisted- pair cables from 0 to over 2km in length. They can generate the necessary G.703 waveshapes for both 75 W coax and 120 W twisted cables. The on-board jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa-bit information. The on-board HDLC controller can be used for Sa-bit links or DS0s. The devices contain a set of internal registers that the user can access to control the operation of the units. Quick access through the parallel control port allows a single controller to handle many E1 lines. The devices fully meet all the latest E1 specifications, including ITU-T G.703, G.704, G.706, G.823, G.732, and I.431, ETS 300 011, 300 233, and 300 166, as well as CTR12 and CTR4. PIN CONFIGURATION FEATURES § Complete E1 (CEPT) PCM-30/ISDN-PRI Transceiver Functionality § On-Board Long- and Short-Haul Line Interface for Clock/Data Recovery and Waveshaping § 32-Bit or 128-Bit Crystal-Less Jitter Attenuator § Frames to FAS, CAS, CCS, and CRC4 Formats § Integral HDLC Controller with 64-Byte Buffers Configurable for Sa Bits, DS0, or Sub-DS0 Operation § Dual Two-Frame Elastic Store Slip Buffers that can Connect to Asynchronous Backplanes up to 8.192MHz § Interleaving PCM Bus Operation § 8-Bit Parallel Control Port that can be used Directly on Either Multiplexed or Nonmultiplexed Buses (Intel or Motorola) § Extracts and Inserts CAS Signaling § Detects and Generates Remote and AIS Alarms § Programmable Output Clocks for Fractional E1, H0, and H12 Applications § Fully Independent Transmit and Receive Functionality § Full Access to Si and Sa Bits Aligned with CRC-4 Multiframe § Four Separate Loopback Functions for Testing Functions § Large Counters for Bipolar and Code Violations, CRC4 Codeword Errors, FAS Word Errors, and E Bits § IEEE 1149.1 JTAG-Boundary Scan Architecture § Pin Compatible with DS2154/52/352/552 SCTs § 3.3V (DS21354) or 5V (DS21554) Supply; Low- Power CMOS § 100-pin LQFP package (14mm x 14mm) ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS21354L 0°C to +70°C 100 LQFP DS21354LN -40°C to +85°C 100 LQFP DS21554L 0°C to +70°C 100 LQFP DS21554LN -40°C to +85°C 100 LQFP DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers www.maxim-ic.com 1 100 Dallas Semiconductor DS21354/DS21554 LQFP TOP VIEW |
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