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DS90C365AMT Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DS90C365AMT Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 12 page  DS90C365A +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-85 MHz General Description The DS90C365A is a pin to pin compatible replacement for DS90C363, DS90C363A and DS90C365. The DS90C365A has additional features and improvements making it an ideal replacement for DS90C363, DS90C363A and DS90C365. family of LVDS Transmitters. The DS90C365A transmitter converts 21 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signal- ing) data streams. A phase-locked transmit clock is transmit- ted in parallel with the data streams over the fourth LVDS link. Every cycle of the transmit clock 21 bits RGB of input data are sampled and transmitted. At a transmit clock fre- quency of 85 MHz, 21 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 223.125 Mbytes/sec. This transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interop- erate with a Falling edge strobe FPDLink Receiver without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces with added Spead Spectrum Clocking support.. Features n Pin-to-pin compatible to DS90C363, DS90C363A and DS90C365 . n No special start-up sequence required between clock/data and /PD pins. Input signals (clock and data) can be applied either before or after the device is powered. n Support Spread Spectrum Clocking up to 100kHz frequency modulation & deviations of ±2.5% center spread or -5% down spread. n “Input Clock Detection” feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high. n 18 to 85 MHz shift clock support n Tx power consumption < 146 mW (typ) @ 85 MHz Grayscale n Tx Power-down mode < 37 uW (typ) n Supports VGA, SVGA, XGA, SXGA(dual pixel), SXGA+(dual pixel), UXGA(dual pixel). n Narrow bus reduces cable size and cost n Up to 1.785 Gbps throughput n Up to 223.125 Megabytes/sec bandwidth n 345 mV (typ) swing LVDS devices for low EMI n PLL requires no external components n Compliant to TIA/EIA-644 LVDS standard n Low profile 48-lead TSSOP package Block Diagram DS90C365A 20100539 Order Number DS90C365AMT See NS Package Number MTD48 PRELIMINARY October 2004 © 2004 National Semiconductor Corporation DS201005 www.national.com |
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