CY7C1355B
CY7C1357B
Document #: 38-05117 Rev. *B
Page 7 of 33
CY7C1355B–Pin Definitions
Name
TQFP
BGA
fBGA
I/O
Description
A0, A1, A
37,36,32,33,
34,35,44,45,
46,47,48,49,
50,81,82,83,
99,100
P4,N4,A2,
C2,R2,A3,
B3,C3,T3,
G4,T4,A5,
B5,C5,T5,
A6,C6,R6
R6,P6,A2,
A9,A10,B2,
B10,P3,P4,
P8,P9,P10,
R3,R4,R8,
R9,R10,R11
Input-
Synchronous
Address Inputs used to select one of the 256K
address locations. Sampled at the rising edge of the
CLK. A[1:0] are fed to the two-bit burst counter.
BWA, BWB
BWC, BWD
93,94,95,96 L5,G5,G3,
L3
B5,A5,A4,
B4
Input-
Synchronous
Byte Write Inputs, active LOW. Qualified with WE to
conduct Writes to the SRAM. Sampled on the rising edge
of CLK.
WE
88
H4
B7
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
ADV/LD
85
B4
A8
Input-
Synchronous
Advance/Load Input. Used to advance the on-chip ad-
dress counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is ad-
vanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK
89
K4
B6
Input-
Clock
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only recog-
nized if CEN is active LOW.
CE1
98
E4
A3
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE2, and CE3 to
select/deselect the device.
CE2
97
B2
B3
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE3 to
select/deselect the device.
CE3
92
B6
A6
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE2 to
select/deselect the device.
OE
86
F4
B8
Input-
Asynchronous
Output Enable, asynchronous input, active LOW.
Combined with the synchronous logic block inside the de-
vice to control the direction of the I/O pins. When LOW,
the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as
input data pins. OE is masked during the data portion of
a write sequence, during the first clock when emerging
from a deselected state, when the device has been dese-
lected.
CEN
87
M4
A7
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW
the Clock signal is recognized by the SRAM. When deas-
serted HIGH the Clock signal is masked. Since deassert-
ing CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
ZZ
64
T7
H11
Input-
Asynchronous
ZZ “Sleep” Input. This active HIGH input places the de-
vice in a non-time critical “sleep” condition with data integ-
rity preserved. During normal operation, this pin can be
connected to VSS or left floating.
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