8K x 9 FIFO, 16K x 9 FIFO
32K x 9 FIFO with Programmable Flags
CY7C470
CY7C472
CY7C474
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 1990 – Revised April 1995
1CY 7C47 4
Features
• 8K x 9, 16K x 9, and 32K x 9 FIFO buffer memory
• Asynchronous read/write
• High-speed 33.3-MHz read/write independent of
depth/width
• Low operating power
—ICC (max.) = 70 mA
• Programmable Almost Full/Empty flag
• Empty, Almost Empty, Half Full, Almost Full, and Full
status flags
• Programmable retransmit
• Expandable in width
• 5V
± 10% supply
• TTL compatible
• Three-state outputs
• Proprietary 0.8-micron CMOS technology
Functional Description
The CYC47X FIFO series consists of high-speed, low-power,
first-in first-out (FIFO) memories with programmable flags and
retransmit mark. The CY7C470, CY7C472, and CY7C474 are
8K, 16K, and 32K words by 9 bits wide, respectively. They are
offered in 600-mil DIP, PLCC, and LCC packages. Each FIFO
memory is organized such that the data is read in the same
sequential order that it was written. Three status pins—Emp-
ty/Full (E/F), Programmable Almost Full/Empty (PAFE), and
Half Full (HF)—are provided to the user. These pins are de-
coded to determine one of six states: Empty, Almost Empty,
Less than Half Full, Greater than Half Full, Almost Full, and
Full.
The read and write operations may be asynchronous; each
can occur at a rate of 33.3 MHz. The write operation occurs
when the write (W) signal goes LOW. Read occurs when read
(R) goes LOW. The nine data outputs go into a high-imped-
ance state when R is HIGH.
The user can store the value of the read pointer for retransmit
by using the MARK pin. A LOW on the retransmit (RT) input
causes the FIFO to resend data by resetting the read pointer
to the value stored in the mark pointer.
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFO to resend the
data. With the mark feature, retransmit can start from any word
in the FIFO.
The CYC47X series is fabricated using a proprietary 0.8-mi-
cron N-well CMOS technology. Input ESD protection is greater
than 2001V and latch-up is prevented by the use of reliable
layout techniques, guard rings, and a substrate bias generator.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
Top View
DIP
W
D8
D3
D2
D1
D0
MARK
PAFE
Q0
Q1
Q2
GND
Vcc
D4
RT
MR
E/F
HF
Q7
R
PLCC/LCC
Top View
Q3
Q8
D5
D6
D7
Q6
Q5
Q4
4
3
2
1
32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
RT
MR
E/F
HF
Q7
D6
Q6
D7
NC
MARK
POINTER
WRITE
POINTER
RESET
LOGIC
RAM ARRAY
8K x 9
16K x 9
32K x 9
DATAINPUTS
(D0–D8)
THREE–
STATE
BUFFERS
DATAOUTPUTS
(Q0–Q8 )
READ
POINTER
FLAG
LOGIC
E/F
PAFE
MR
RT
D2
D1
D0
MARK
PAFE
Q0
Q1
NC
Q2
7C470–1
7C470–2
7C470–3
7C470
7C472
7C474
7C470
7C472
7C474
W
HF
MARK
R
PROGRAMMABLE
FLAG REGISTER
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