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CY28347 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part No. CY28347
Description  Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28347 Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY28347
Document #: 38-07352 Rev. *C
Page 6 of 22
4
1
17
PCI5
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
3
1
15
PCI4
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
2
1
14
PCI3
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1
1
12
PCI2
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
0
1
11
PCI1
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
Byte 3: AGP/Peripheral Clocks Register
Bit
@Pup
Pin#
Name
Description
7
0
21
24_48M
“0” = pin 21 output is 24 MHz. Writing a “1” into this register
asynchronously changes the frequency at pin 21 to 48 MHz.
6
1
20
48MHz
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
5
1
21
24_48M
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
4
0
6,7,8
DASAG1
Programming these bits allow shifting skew of the AGP(0:2)
signals relative to their default value. See Table 7.
3
0
6,7,8
DASAG0
2
1
Reserved, set = 1.
1
1
7
AGP1
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
0
1
6
AGP0
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
Byte 4: Peripheral Clocks Register
Bit
@Pup
Pin#
Name
Description
7
1
20
48M
1 = strength x 1. 0= strength x 2
1 = strength x 1. 0= strength x 2
6
1
21
24_48M
1 = strength x 1. 0= strength x 2
1 = strength x 1. 0= strength x 2
5
0
6,7,8
DARAG1
Programming these bits allow modifying the frequency ratio of
the AGP(2:0), PCI(6:1, F) clocks relative to the CPU clocks. See
Table 8.
4
0
6,7,8
DARAG0
3
1
1
REF0
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
2
1
56
REF1
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state. (K7 Mode only.)
1
1
1
REF0
1 = strength x 1. 0 = strength x 2
0
1
56
REF1
1 = strength x 1. 0 = strength x 2 (K7 Mode only)
Byte 2: PCI Clock Register (continued)
Bit
@Pup
Pin#
Name
Description
Table 7. Dial-a-Skew™ AGP(0:2)
DASAG (1:0)
AGP(0:2) Skew Shift
00
Default
01
–280 ps
10
+280 ps
11
+480 ps


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