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CXA3562AR Datasheet(PDF) 3 Page - Sony Corporation |
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CXA3562AR Datasheet(HTML) 3 Page - Sony Corporation |
3 / 24 page – 3 – CXA3562AR Pin Description Pin No. Symbol I/O Standard voltage level Equivalent circuit Description VDD 140k 60k 60k 100µ 1k 1k 140k 8k GND 2 3 VDD GND 192 50k 4 PECL differential (amplitude 0.4V or more between VDD to 2V) or TTL input High: ≥2.0V Low: ≤0.8V High: ≥2.0V Low: ≤0.8V High: ≥2.0V Low: ≤0.8V VDD GND 192 50k 5 VDD GND 192 50k 9 8 7 6 VDD VCC GND 30k 20µ 16 VDD VCC GND 30k 10µ 17 1 to 5.0V 0 to 5.0V I SIG_OFST 17 I SIG.C 16 I POSCTR0 POSCTR1 POSCTR2 POSCTR3 6 7 8 9 I SHST 5 I FRP 4 I MCLK MCLKX 2 3 Dot clock input. PECL differential input or TTL input. For TTL input, input to MCLK and connect MCLKX to GND through a capacitor. LCD panel AC drive inversion timing input. High: inverted Low: non-inverted See the Timing Chart. Internal sample-and-hold timing circuit reset pulse input. This pin is also used as the offset cancel level insertion timing input. A reset is applied to the internal timing generator at the falling edge. Output phase adjustment. The output phase is adjusted in MCLK period units when SL_DAT (Pin 72) is high, and in 1/2 MCLK period units when SL_DAT is low. Signal center voltage (inversion folded voltage) adjustment input. The SH_OUT output center voltage can be adjusted in the range from 7.0 to 8.0V. Output signal offset adjustment from signal center voltage. The SH_OUT output 100% white level (at 3FF input) voltage can be adjusted in the range from 0 to 1V from the center voltage. |
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