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CM3121 Datasheet(PDF) 2 Page - California Micro Devices Corp

Part # CM3121
Description  Dual Linear Voltage Regulator for DDR-I and DDR-II Memory
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Manufacturer  CALMIRCO [California Micro Devices Corp]
Direct Link  http://www.calmicro.com
Logo CALMIRCO - California Micro Devices Corp

CM3121 Datasheet(HTML) 2 Page - California Micro Devices Corp

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© 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
11/12/04
CM3121
PRELIMINARY
Functional Description
The CM3121 provides power for DDR-I/DDR-II memo-
ries from two voltage regulators on-chip. There is an
over-temperature thermal shutdown if any of the regu-
lators overheat. Each regulator also has reverse cur-
rent protection in the event of any being shut down.
The VDDQ linear regulator can provide 2.5V/1.8V for
DDR-I/-II memory at up to 1.5A. An external feedback
resistor divider R1 and R2, when connected to the
SENSE_VDDQ pin, enables selection of VDDQ output
voltages from 2.2V to 2.8V for use with DDR-I memo-
ries requiring other than 2.5V for VDDQ (see Figure 5).
In this mode, the voltage on VDDQ is detemined as fol-
lows:
VDDQ = 1.25V x
When SENSE_VDDQ is connected to GND or left open,
VDDQ is fixed at 2.50V (and VTT at 1.25V). For DDR-II
operation, VDDQ can be set from 1.7V to 1.9V. The VTT
regulator is a linear source-sink regulator powered
from the VDDQ output that supplies the VTT supply
required by DDR-I memory termination resistors. This
regulator sinks or sources up to 0.5A. The VTT output
voltage accurately tracks VDDQ/2 to 1%. When there is
no VCC provided, VTT is powered down and its output
is 0V. This regulator has overload current limiting of
0.6A minimum.
The EN_DDR pin when set active low enables the
CM3121 to operate in normal mode with VDDQ and VTT
active. When EN_DDR is high, the CM3121 is disabled
and both VDDQ and VTT are set to 0V.
The FAULT output is normally at logic high but when
an overcurrent occurs on either VDDQ or VTT outputs,
FAULT goes active low, and remains low as long as
the overcurrent fault persists. Also if the chip goes into
thermal overload, or the input voltage VCC drops suffi-
ciently that the chip goes into Under Voltage Lock-Out
mode (UVLO), FAULT goes active low, and remains
low as long as the condition persists.
(R1+R2)
R2
----------------------
PIN DESCRIPTIONS
LEAD
NAME
DESCRIPTION
1VCC
Input supply.
2VDDQ
VDDQ output.
3VTT
VTT output for termination resistors or VREF
4
GND
Ground reference.
5
EN_DDR
Enable DDR power. Active low input.
6
SENSE_VTT
Sense input for VTT rail adjustment.
7FAULT
Overcurrent Fault / UVLO indication, active low output.
8
SENSE_VDDQ
Sense input for VDDQ rail adjustment.
PAD
GND
Tied to ground reference.
PACKAGE / PINOUT DIAGRAM
Note: This drawing is not to scale.
8-Lead PSOP
1
2
3
4
8
7
6
5
VCC
VDDQ
VTT
GND
SENSE_VDDQ
FAULT
SENSE_VTT
EN_DDR
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