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AHA4012B-006 Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers |
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AHA4012B-006 Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers |
10 / 28 page Page 6 of 24 PS4012B-0100 Advanced Hardware Architectures, Inc. 2.6 RESET AND INITIALIZATION SEQUENCE Reset and initialization first requires pulling the RSTN low signal for at least two clocks while the DSIN and DSON signals are held inactive, i.e., high. Following this sequence, the six internal registers, referred to as “Initialization Registers” are strobed by DSIN. These bytes are loaded in order of 1 through 6. The RSTN must be active low for at least two clocks before the first initialization byte is strobed in and remain active for at least one clock after the final byte. RSTN must be high for at least two clocks before the first message byte can be strobed into the device. For a detailed timing diagram, see Figure 8: Reset and Initialization Timing. The chip must be reset and initialized any time a reset is necessary. Caveat: All six registers must be initialized correctly for proper operation of the chip. The device has no provisions for reading back Initialization Register settings. This sequence must be used if the device needs to be reset or any one register needs updating, i.e., all registers must be reinitialized for a change to any one register. 2.6.1 INITIALIZATION REGISTERS BYTE 1, ERASURE MULTIPLIER: [7:0] Multiplier value that must be programmed as shown in Appendix A. The table shows a value to be programmed corresponding to the block length selected. BYTE 2, ERROR THRESHOLD: [4:0] The threshold for determining uncorrectability of a data block, and the number of check bytes allocated for correction-only purposes. When not using erasures set to the same value as BYTE 3, CHECK BYTES. Minimum value of 0x02 sets the Threshold to 2 and 0x14 sets to the maximum, 20. [6:5] Reserved. Set to 0. [7] Not used. Don't care. BYTE 3, CHECK BYTES: [4:0] Number of check bytes in RS code, R. Minimum setting of 0x02 indicates two check bytes for R = 2 and 0x14 indicates the maximum of 20. [6:5] Reserved. Set to 0. [7] Not used. Don't care. BYTE 4, MESSAGE BYTES: [7:0] Number of message bytes in code, K. Minimum setting of 0x01 indicates 1 byte, setting to 0xFD indicates the maximum 253 message bytes. BYTE 5, BLOCK LENGTH: [7:0] Number of bytes in block, N. Setting to 0x03 indicates 3 bytes, setting to 0xFF indicates 255 bytes. BYTE 6, CONTROL BYTE: [0] RES Reserved. Set to 0. [1] NOPAR Parity Symbol Control When set to 0, check bytes are output following the message bytes. When set to 1, check bytes are not output following the message bytes. Correction will be done regardless depending upon the bit 4, RAW, setting. [3:2] RES Reserved. Set both bits t o1. [4] RAW Raw Data When set to 0, outputs corrected data. When set to 1, outputs raw uncorrected input data. [5] ERC Erasure Rejection Control. This bit is only used by the device when the Erasures exceed the ERROR THRESHOLD or R settings. This bit is ignored when the Erasures are less than or equal to ERROR THRESHOLD or R. When set to 0, if Erasures are greater than the ERROR THRESHOLD or R then erasures are discarded and full correction is performed. The block is flagged uncorrectable and the output CRTN will be high during the first message byte of the block. When set to 1, if Erasures are greater than ERROR THRESHOLD or R then erasures are discarded and full correction is performed. The output CRTN will be high only when the block is uncorrectable. [7:6] Reserved, Set to 0. |
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