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74HC137D Datasheet(PDF) 1 Page - NXP Semiconductors

Part No. 74HC137D
Description  3-to-8 line decoder, demultiplexer with address latches inverting
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74HC137D Datasheet(HTML) 1 Page - NXP Semiconductors

 
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1.
General description
The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power
Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC
standard no. 7A.
The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address
inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit
storage latch. When the latch is enabled (LE = LOW), the 74HC137 acts as a 3-to-8 active
LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present
at the inputs before this transition, is stored in the latches. Further address changes are
ignored as long as LE remains HIGH.
The output enable input (E1 and E2) controls the state of the outputs independent of the
address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.
The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state
systems and strobed (stored address) applications in bus oriented systems.
2.
Features
s Combines 3-to-8 decoder with 3-bit latch
s Multiple input enable for easy expansion or independent controls
s Active LOW mutually exclusive outputs
s Low-power dissipation
s Complies with JEDEC standard no. 7A
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s Multiple package options
s Specified from
−40 °Cto+80 °C and from −40 °C to +125 °C.
74HC137
3-to-8 line decoder, demultiplexer with address latches;
inverting
Rev. 03 — 11 November 2004
Product data sheet


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