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74ACT125MTR Datasheet(PDF) 1 Page - STMicroelectronics |
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74ACT125MTR Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 9 page 1/9 July 2001 s HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C s COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) s 50 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74ACT125 is an advanced high-speed CMOS QUAD BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. This device require the 3-STATE control input G to be set high to place the output in high impedance state. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74ACT125 QUAD BUS BUFFERS (3-STATE) PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP 74ACT125B SOP 74ACT125M 74ACT125MTR TSSOP 74ACT125TTR TSSOP DIP SOP |
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