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74AC11109 Datasheet(PDF) 5 Page - Texas Instruments |
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74AC11109 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 7 page  54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS450 – MARCH 1987 – REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 PARAMETER MEASUREMENT INFORMATION 50% VCC 50% 50% 50% VCC VCC 0 V 0 V th tsu VOLTAGE WAVEFORMS Data Input tPLH tPHL tPHL tPLH VOH VOH VOL VOL 50% 50% VCC 0 V 50% VCC 50% VCC Input (see Note B) Out-of-Phase Output In-Phase Output Timing Input (see Note B) 50% VCC VOLTAGE WAVEFORMS VCC 0 V 50% 50% tw VOLTAGE WAVEFORMS Input LOAD CIRCUIT From Output Under Test CL = 50 pF (see Note A) 500 Ω NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms |
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