NCP81391, NCP81391A

www.onsemi.com

2

Figure 2. Simplified Block Diagram

DEAD

TIME

CNTRL

LEVEL

SHIFT

UVLO

GLF

VCC

CGND

EN

PWM

LOGIC

45k

VCCD

BST

VIN

PHASE

LEVEL

SHIFT

45k

VSWH

PGND

Temp

Sense

SHUTDOWN

Clip

GH

ZCD_EN#

VSWH

3.84V

For NCP81391/

No resistor for

NCP81391A

For NCP81391/

No TSD for

NCP81391A

3.84V

GLD

Table 1. PIN LIST AND DESCRIPTIONS

Pin No.

Symbol

Description

1

PHASE

Bootstrap Capacitor Return

2

PGND2

Power Ground

3

CGND

Signal Ground

4

EN

Enable. There is a pull−down resistor to CGND for the NCP81391. No pull−down resistor for NCP81391A.

5

PWM

PWM Control Input:

PWM = High

³ HS FET is on, LS FET is off

PWM = Mid

³ HS FET is off, LS FET is off

PWM = Low, ZCD_EN# = High

³ HS FET is off, LS FET is on

PWM = Low, ZCD_EN# = Low

³ HS FET is off, LS FET is off when zero current is detected

6

ZCD_EN#

Zero Current Detect Control. When this pin is at logic low, low−side FET will turn off when zero inductor

current is detected (after a minimum blanking/de−bounce time). There is an internal pull−up resistor.

7

VCC

Control Power Supply Input

8

VCCD

Driver Power Supply Input

9

NC9

No Connect

10

BST

Bootstrap Supply Voltage. Connect a MLCC capacitor of at least 0.1

mF from this pin to PHASE.

11

GH

High−Side MOSFET Gate Access. Leave floating.

12

NC12

No Connect

13

VIN13

Conversion Supply Power Input

14

VIN14

Conversion Supply Power Input

15

VIN15

Conversion Supply Power Input