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SC16C650B Datasheet(PDF) 20 Page - NXP Semiconductors |
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SC16C650B Datasheet(HTML) 20 Page - NXP Semiconductors |
20 / 51 page Philips Semiconductors SC16C650B UART with 32-byte FIFOs and IrDA encoder/decoder Product data Rev. 03 — 10 December 2004 20 of 51 9397 750 14451 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. • FIFO status will also be reflected in the user accessible ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. • The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C650B in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). • LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. • LSR[1:4] will provide the type of errors encountered, if any. • LSR[5] will indicate when the transmit FIFO is empty. • LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty. • LSR[7] will indicate any FIFO data errors. 2 IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a fully assembled receive character is transferred from RSR to the RHR/FIFO, i.e., data ready, LSR[0]. Logic 0 = Disable the receiver line status interrupt (normal default condition). Logic 1 = Enable the receiver line status interrupt. 1 IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the THR is empty, and is associated with LSR[1]. Logic 0 = Disable the transmitter empty interrupt (normal default condition). Logic 1 = Enable the transmitter empty interrupt. 0 IER[0] Receive Holding Register interrupt. This interrupt will be issued when the FIFO has reached the programmed trigger level, or is cleared when the FIFO drops below the trigger level in the FIFO mode of operation. Logic 0 = Disable the receiver ready interrupt (normal default condition). Logic 1 = Enable the receiver ready interrupt. Table 9: Interrupt Enable Register bits description…continued Bit Symbol Description |
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