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XR16L2551 Datasheet(PDF) 7 Page - Exar Corporation |
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XR16L2551 Datasheet(HTML) 7 Page - Exar Corporation |
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7 / 48 page  áç áç áç áç XR16L2551 REV. 1.0.0 LOW VOLTAGE DUART WITH POWERSAVE 7 1.0 PRODUCT DESCRIPTION The XR16L2551 (L2551) provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The L2551 represents such an integration with greatly enhanced features. The L2551 is fabricated with an advanced CMOS process. Transmit and Receive FIFOs (16 Bytes each) The L2551 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The L2551 is designed to work with high speed modems and shared network environments, that require fast data processing time. Increased performance is realized in the L2551 by the transmit and receive FIFO’s. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in 93 microseconds (This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the external CPU will have to service the receive FIFO less than every 100 microseconds. However with the 16 byte FIFO in the L2551, the data buffer will not require unloading/loading for 1.53 ms. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger interrupt levels is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. Data Bus Interface, Intel or Motorola Type The L2551 provides a single host interface for the 2 UARTs and supports Intel or Motorola microprocessor (CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#, IOW# and CSA# or CSB# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#, CS# and A3 signals for data bus transactions. Few data bus interface signals change their functions depending on user’s selection, see pin description for details. The Intel and Motorola bus interface selection is made through the 16/68# pin (pin 24 for 48-TQFP package and pin 17 for 32-QFN package). Enhanced Features The XR16L2551 integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its features set is compatible to the XR16L2550 device but offers Intel or Motorola data bus interface and PowerSave to isolate the data bus interface during Sleep mode. Each UART is independently controlled having its own set of device configuration registers. The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, each UART channel has automatic RTS/CTS hardware flow control, automatic Xon/Xoff and special character software flow control, infrared encoder and decoder (IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 3.125 Mbps at 5V with a 50 MHz external clock. The rich feature set of the L2551 is available through internal registers. Selectable receive FIFO trigger levels, selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power on reset or an external reset (and operating in 16 or Intel Mode), the L2551 is functionally and software compatible with the previous generation ST16C2450 and ST16C2550. |
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