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S1D2512X01-A0B0 Datasheet(PDF) 25 Page - Samsung semiconductor

Part # S1D2512X01-A0B0
Description  DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
24
Sync Inputs
Both H/HVin and Vsyncin inputs are TTL compatible trigger with Hysteresis to avoid erratic detection.
Both inputs include a pull up register connected to VDD.
Sync Processor Output
The sync processor indicates on the HLOCKOUT Pin whether 1st PLL is locked to an incoming horizontal sync.
HLOCKOUT is a TTL compatible CMOS output. Its level goes to high when locked. In the same time the D8 bit of
the status register is set to 0. This information is mainly used to trigger safety procedures (like reducing B+ value)
as soon as a change is detected on the incoming sync. Further to this, it may be used in an automatic procedure
for free running frequency(fo) adjustment.
Sending the desired fo on the sync input and progressively decreasing the free running frequent I2C register value
(address 02), the HLOCKOUT Pin will go high as soon as the proper setting is reached. Setting the free running
frequency this way allows to fully exploit the S1D2512X01 horizontal frequency range.
HORIZONTAL PART
Internal input conditions
Horizontal part is internally fed by Synchro processor with a digital signal corresponding to horizontal Synchro
pulses or to TTL composite input.
concerning the duty cycle of the input signal, the following signals (positive or negative) may be applied to the
circuit.
Using internal integration, both signals are recognized on condition that Z/T < 25%, Synchronization occurs on the
leading edge of the internal sync signal. The minimum value of Z is 0.7
µs.
An other integration is able to extract vertical pulse of composite Synchro if duty cycle is more than 25% (typically
d = 35%) (see 7)
The last feature performed is the equalizing pulses removing to avoid parasitic pulse on phase comparator input
which is intolerant to wrong or missing pulse.
Z
T
Z
d
d
c
TRAMEXT


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