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NB100LVEP224 Datasheet(PDF) 1 Page - ON Semiconductor

Part No. NB100LVEP224
Description  2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB100LVEP224 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2003
June, 2003 - Rev. 4
1
Publication Order Number:
NB100LVEP224/D
NB100LVEP224
2.5V/3.3V 1:24 Differential
ECL/PECL Clock Driver with
Clock Select and Output
Enable
The NB100LVEP224 is a low skew 1-to-24 differential clock
driver, designed with clock distribution in mind, accepting two clock
sources into an input multiplexer. The part is designed for use in low
voltage applications which require a large number of outputs to drive
precisely aligned low skew signals to their destination. The two clock
inputs are differential ECL/PECL and they are selected by the
CLK_SEL pin. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE) is synchronous
ensuring the outputs will only be enabled/disabled when they are
already in LOW state (See Figure 4).
The NB100LVEP224 guarantees low output-to-output skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. In any differential output, the same bias and
termination scheme is required. Unused output pairs should be left
unterminated (open) to “reduce power and switching noise as much as
possible.” Any unused single line of a differential pair should be
terminated the same as the used line to maintain balanced loads on the
differential driver outputs. The wide VIHCMR specification allows
both pair of CLOCK inputs to accept LVDS levels.
The NB100LVEP224, as with most other ECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP224 to be used for high performance clock distribution in
+3.3 V or +2.5 V systems. Single-ended CLK input operation is
limited to a VCC ≥ 3.0 V in LVPECL mode, or VEE ≤ -3.0 V in NECL
mode. In a PECL environment, series or Thevenin line terminations
are typically used as they require no additional power supplies. For
more information on PECL terminations, designers should refer to
Application Note AND8020/D.
20 ps Typical Output-to-Output Skew
75 ps Typical Device-to- Device Skew
Maximum Frequency > 1 GHz
650 ps Typical Propagation Delay
LVPECL Mode Operating Range:
VCC = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = -2.375 V to -3.8 V
Internal Input Pulldown Resistors
Q Output will Default Low with Inputs Open or at V
EE
Thermally Enhanced 64-Lead LQFP
CLOCK Inputs are LVDS-Compatible; Requires External 100 W
LVDS Termination Resistor
64-LEAD LQFP
CASE 848G
THERMALLY ENHANCED
FA SUFFIX
Device
Package
Shipping
ORDERING INFORMATION
NB100LVEP224FA
LQFP-64
160 Units/Tray
NB100LVEP224FAR2 LQFP-64 1500/Tape & Reel
MARKING
DIAGRAM*
*For additional information, see Application Note
AND8002/D
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
NB100
LVEP224
AWLYYWW
64
1
64
1
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