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W320-04H Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. W320-04H
Description  200-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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W320-04H Datasheet(HTML) 3 Page - Cypress Semiconductor

 
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W320-04
Document #: 38-07010 Rev. *B
Page 3 of 18
Function Table[1]
S2
S1
S0
CPU
(MHz)
3V66[0:1]
(MHz)
66BUFF[0:2]/
3V66[2:4]
(MHz)
66IN/3V66_5
(MHz)
PCI_F/PCI
(MHz)
REF0(MHz)
USB/DOT
(MHz)
Notes:
1
0
0
66 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
2, 3, 4
1
0
1
100 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
2, 3, 4
1
1
0
200 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
2, 3, 4
1
1
1
133 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
2, 3, 4
0
0
0
66 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
2, 3, 4
0
0
1
100 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
2, 3, 4
0
1
0
200 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
2, 3, 4
0
1
1
133 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
2, 3, 4
Mid
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1, 5
Mid
0
1
TCLK/2
TCLK/4
TCLK/4
TCLK/4
TCLK/8
TCLK
TCLK/2
7, 8, 5
Mid
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Mid
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Swing Select Functions
Mult0
Board Target Trace/Term Z
Reference R, IREF = VDD/(3*Rr)
Output Current
VOH @ Z
050
Rr = 221 1%, IREF = 5.00 mA
IOH = 4*IREF
1.0V @ 50
150
Rr = 475 1%, IREF = 2.32 mA
IOH = 6*IREF
0.7V @ 50
Clock Driver Impedances
Impedance
Buffer Name
VDD Range
Buffer Type
Min.
Typ.
Max.
CPU, CPU#
Type X1
50
REF
3.135–3.465
Type 5
12
30
55
PCI, 3V66, 66BUFF
3.135–3.465
Type 5
12
30
55
USB
3.135–3.465
Type 3A
12
30
60
DOT
3.135–3.465
Type 3B
12
30
60
Clock Enable Configuration
PWR_DWN# CPU_STOP#
PCI_STOP#
CPU
CPU#
3V66
66BUFF
PCI_F
PCI
USB/DOT
VCOS/
OSC
0
X
X
IREF*2
FLOAT
LOW
LOW
LOW
LOW
LOW
OFF
1
0
0
ON
FLOAT
ON
ON
ON
OFF
ON
ON
1
0
1
ON
LOW
ON
ON
ON
ON
ON
ON
1
1
0
ONON
ONON
ON
OFF
ON
ON
1
1
1
ONON
ONON
ON
ON
ON
ON
Note:
1.
TCLK is a test clock driven in on the XTALIN input in test mode.
2.
“Normal” mode of operation
3.
Range of reference frequency allowed is min. = 14.316, nom. = 14.31818 MHz, max. = 14.32 MHz.
4.
Frequency accuracy of 48 MHz must be +167PPM to match USB default.
5.
Mid. is defined a Voltage level between 1.0V and 1.8V for three-level input functionality. Low is below 0.8V. High is above 2.0V.
6.
Required for DC output impedance verification.
7.
These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.


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