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CY28341-2 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY28341-2
Description  Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28341-2 Datasheet(HTML) 3 Page - Cypress Semiconductor

 
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CY28341-2
Document #: 38-07471 Rev. *B
Page 3 of 19
11
SELSDR_DDR#/
PCI1
VDDPCI
I/O
PD
Power-on Bidirectional Input/Output. At power-up, SELSDR_DDR is the
input. When the power supply voltage crosses the input threshold voltage,
SELSDR_DDR state is latched and this pin becomes PCI clock output.
SelSDR_DDR#.= 0, DDR Mode. SelSDR_DDR#.= 1, SDR Mode.
21
FS2/24_48M
VDD48M
I/O
PD
Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When
the power supply voltage crosses the input threshold voltage, FS2 state is
latched and this pin becomes 24_48M, a SIO programmable clock output.
6
AGP0
VDDAGP
O
AGP Clock Output. Is synchronous to CPU clocks. See Table 1
8
AGP2
VDDAGP
O
AGP Clock Output. Is synchronous to CPU clocks. See Table 1
25
IREF
I
Current reference programming input for CPU buffers. A precise resistor
is attached to this pin, which is connected to the internal current reference.
28
SDATA
I/O
Serial Data Input. Conforms to the Phillips I2C specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.
27
SCLK
I
Serial Clock Input. Conforms to the Philips I2C specification.
26
PD#/SRESET#
I/O
PU
Power-down Input/System Reset Control Output. If Byte6 Bit7 = 0(default),
this pin becomes a SRESET# open drain output. See system reset description.
If Byte6Bit7 = 1, this pin becomes PD# input with an internal pull-up. When
PD# is asserted low, the device enters power down mode. See power
management function.
45
BUF_IN
If SelSDR_DDR#.= 0, 2.5V CMOS type input to the DDR differential
buffers. If SelSDR_DDR#.= 1, 3.3V CMOS type input to the SDR buffer.
46
FBOUT
If SelSDR_DDR#.= 0, 2.5V single ended SDRAM buffered output of the
signal applied at BUF_IN. It is in phase with the DDRT(0:5) signals.If
SelSDR_DDR#.= 1, 3.3V single ended SDRAM buffered output of the signal
applied at BUF_IN. It is in phase with the SDRAM(0:11) signals
5
VDDAGP
3.3V power supply for AGP clocks
51
VDDC
3.3V power supply for CPUT/C clocks
16
VDDPCI
3.3V power supply for PCI clocks
55
VDDR
3.3V power supply for REF clock
50
VDDI
2.5V power supply for CPUCS_T/C clocks
22
VDD_48M
3.3V power supply for 48M
23
VDD
3.3V Common power supply
34,40
VDDD
If SelSDR_DDR#.= 0, 2.5V power supply for DDR clocksIf
SelSDR_DDR#.= 1, 3.3V power supply for SDR clocks.
9
VSSAGP
Ground for AGP clocks
13
VSSPCI
Ground for PCI clocks
54
VSSC
Ground for CPUT/C clocks
33,39
VSSD
Ground for DDR clocks
19
VSS_48M
Ground for 48M clock
47
VSSI
Ground for ICPUCS_T/C clocks
2
VSSR
Ground for REF
24
VSS
Common Ground
Pin Description [2] (continued)
Pin Number
Pin Name
PWR
I/O
Pin Description


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