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CY28341-2 Datasheet(PDF) 16 Page - Cypress Semiconductor

Part No. CY28341-2
Description  Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28341-2 Datasheet(HTML) 16 Page - Cypress Semiconductor

 
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CY28341-2
Document #: 38-07471 Rev. *B
Page 16 of 19
TR/TF
CPUT/C Rise and Fall Times
175
700
175
700
175
700
ps 24
Rise/Fall Matching
20%
20%
20%
24,26
∆ T
R/TF
Rise/Fall Time Variation
125
125
125
ps 8,24,16
TSKEW
CPUCS_T/C to CPUT/C Clock Skew
0
200
0
150
0
200
ps 8,18,15,16
TCCJ
CPUT/C Cycle to Cycle Jitter
–150
+150
–150
+150
–200
+200
ps 8,18,15,16
VCROSS
Crossing Point Voltage at 0.7V Swing
280
430
280
430
280
430
mV 16
P4 Mode CPU at 1.0V
TDC
CPUT/C Duty Cycle
45
55
45
55
45
55
% 8,9,15
TPERIOD
CPUT/C Period
9.85
10.2
7.35
7.65
4.85
5.1
nS 8,9,15
Differential
TR/TF
CPUT/C Rise and Fall times
175
467
175
467
175
467
ps 7,14,27
TSKEW
CPUCS_T/C to CPUT/C Clock Skew
0
200
0
150
0
200
0
8,14,11
TCCJ
CPUT/C Cycle to Cycle Jitter
–150
+150
–150
+150
–200
+200
ps 8,14,11
VCROSS
Crossing Point Voltage at 1V Swing
510
760
510
760
510
760
mV 27
SE-DeltaSlew Absolute Single-ended Rise/Fall
Waveform Symmetry
325
325
325
ps 26
K7 Mode
TDC
CPUOD_T/C Duty Cycle
45
55
45
55
45
55
% 8,9
TPERIOD
CPUOD_T/C Period
9.98
10.5
7.5
8.0
5
5.5
ns 8,9
TLOW
CPUOD_T/C Low Time
2.8
1.67
2.8
ns 8,9
TF
CPUOD_T/C Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns 8,13
TSKEW
CPUCS_T/C to CPUT/C Clock Skew
0
200
0
150
0
200
0
8,14,11
TCCJ
CPUOD_T/C Cycle-to-Cycle Jitter
–150
+150
–150
+150
–200
+200
ps 8,9
VD
Differential Voltage AC
.4
Vp+.6V
.4
Vp+.6V
.4
Vp+.6V
V
23
VX
Differential Crossover Voltage
500
1100
500
1100
500
1100
mV 23
CHIPSET CLOCK
TDC
CPUCS_T/C Duty Cycle
45
55
45
55
45
55
% 7,8,9
TPERIOD
CPUCS_T/C Period
10.0
10.5
15
15.5
10.0
10.5
ns 7,8,9
TR / TF
CPUCS_T/C Rise and Fall Times
0.4
1.6
0.4
1.6
0.4
1.6
ns 7,8,13
VD
Differential Voltage AC
.4
Vp+.6V
.4
Vp+.6V
.4
Vp+.6V
V
24
VX
Differential Crossover Voltage
0.5*VD
DI–0.2
0.5*VDDI
+0.2
0.5*VD
DI–0.2
0.5*VD
DI+0.2
0.5*VD
DI–0.2
0.5*VD
DI+0.2
V11
AGP
TDC
AGP(0:2) Duty Cycle
45
55
45554555
% 7,8,9
TPERIOD
AGP(0:2) Period
15
16
15
16
15
16
ns 7,8,9
THIGH
AGP(0:2) High Time
5.25
5.25
5.25
ns 8,21
TLOW
AGP(0:2) Low Time
5.05
5.05
5.05
ns 8,10
TR / TF
AGP(0:2) Rise and Fall Times
0.4
1.6
0.4
1.6
0.4
1.6
ns 8,13
Notes:
17. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and
between 20% and 80% for differential signals.
18. This measurement is applicable with Spread ON or spread OFF.
19. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals).
20. Time specified is measured from when all VDDs reach their respective supply rail (3.3V and 2.5V) till frequency output is stable and operating within specs.
21. The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same.
22. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its comple-
mentary DDRC (and CPUCS_C) one.
23. Measured at VX between the rising edge and the following falling edge of the signal.
24. Measured from VOL = 0.175V to VOH = 0.525V.
25. Measurement taken from differential waveform, from –0.35V to +0.35V.
26. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as “the instantaneous
difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is
designed for waveform symmetry.
27. Measured in absolute voltage, i.e., single-ended measurement.
AC Parameters (continued)
Parameter
Description
100 MHz
133 MHz
200 MHz
Unit
Notes
Min.
Max.
Min.
Max
Min.
Max.


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