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CY28341-2 Datasheet(PDF) 10 Page - Cypress Semiconductor

Part No. CY28341-2
Description  Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28341-2 Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY28341-2
Document #: 38-07471 Rev. *B
Page 10 of 19
P4 Processor SELP4_K7# = 1
Power-down Assertion (P4 Mode):
When PD# is sampled low by two consecutive rising edges of
CPU# clock then all clock outputs except CPU clocks must be
held low on their next high to low transition. CPU clocks must
be held with the CPU clock pin driven high with a value of 2 x
Iref, and CPU# undriven. Note that Figure 1 shows CPU =
133 MHz. This diagram and description are applicable for all
valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state
of internal logic, stopping and holding the REF clock outputs
in the LOW state may require more than one clock cycle to
complete.
S y s t e m
r u nn i n g
w i t h
o r ig in a lly s e le c t e d
f r eq ue nc y v i a
h a rd w a re
s t ra p p i n g .
R e cei v e
F r eq ue ncy
C h ang e
R e qu est v i a
SM Bu s
By t e
4
o r V i a
D i a l -
a - f r eq ue nc y ?
S t a r t i n te r n a l w a tc h
d o g
ti m e r .
W a t c h
D o g
t i m e
ou t ?
T u r n
o f f w a t c h
do g
t i m e r .
K e e p
n e w
fre q u e n c y s e tti n g . S e t W D
a l a r m
bi t ( b y t e
1 2 , b i t 4 ) t o
' ' 0'
1 )
S e nd
a n o t h e r 3m S
l o w
pu l s e
on
S R E S E T
2 )
R e la t c h
o r ig in a l h a r d w a r e
s t r a p p in g
s e l e c t io n
fo r r e t u rn
t o
o r i g i n a l fre q u e n c y s e tti n g s .
3 ) S e t W D
A l a r m
b i t (b y t e
1 2 , B i t 4 ) to
" 1 "
4 ) S t a r t W D
ti m e r
F r eq ue nc y w i l l c h a n g e
bu t S y s t e m
S e l f
R e cov e r y no t a p p l i c ab l e
( n o
t i m e
s t am p
s e l e c t e d
an d
by t e
12 , b i t ( 3: 0) i s s t i l l =
" 0 000 "
No
No
Ye s
No
No
Ye s
SM Bu s
b y t e
1 2
t i m e
ou t st am p
d i s a bl ed ?
Is S M B u s
B y te
9 , ti m e
o u t
s t am p
en abl e d
- ( b y t e
12 , b i t
(3 :0 )
0 0 0 0 ) ?
C h an ge
t o
a
n e w
f r eq ue nc y
Ye s
1 ) Se n d
S R ES ET
pu l s e
2) S e t W D
bi t
( b y t e1 2, bi t 4 ) t o
' 1 '
3 ) S t a r t W D
t i m e r
Ye s
W a tc h
D o g
ti m e
o u t?
No
Ye s
S M B u s b y te
9
ti m e
o u t
st am p
d i s a bl ed , B y t e
1 2 , bi t ( 3 : 0) =
( 0 00 0) ?
Ye s
No
Figure 1. Watchdog Recovery Clock
PCI 3 3 M H z
PW R D W N #
CPUT 1 3 3 M Hz
C P U T # 13 3M H z
R E F 14.31 8M H z
USB 4 8 M H z
S D RAM 1 3 3 M Hz
D DRT 1 3 3 M Hz
DDR C 1 3 3 M Hz
A G P 66M H z
Figure 2. Power-down Assertion Timing Waveform (in P4 mode)


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