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CY28341-2 Datasheet(PDF) 9 Page - Cypress Semiconductor

Part No. CY28341-2
Description  Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28341-2 Datasheet(HTML) 9 Page - Cypress Semiconductor

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CY28341-2
Document #: 38-07471 Rev. *B
Page 9 of 19
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is enabled/disabled via SMBus register Byte
1, Bit 7.
System Self Recovery Clock Management
This feature is designed to allow the system designer to
change frequency while the system is running and reboot the
operation of the system in case of a hang up due to the
frequency change.
When the system sends an SMBus command requesting a
frequency change through Byte 4 or through bytes 13 and 14,
it must have previously sent a command to byte 12, for
selecting which time out stamp the Watchdog must perform,
otherwise the System Self Recovery feature will not be appli-
cable. Consequently, this device will change frequency and
then the Watchdog timer starts timing. Meanwhile, the system
BIOS is running its operation with the new frequency. If this
device receives a new SMBus command to clear the bits origi-
nally programmed in Byte 12, bits (3:0) (reprogram to 0000),
before the Watchdog times out, then this device will keep
operating in its normal condition with the new selected
frequency. If the Watchdog times out the first time before the
new SMBus reprograms Byte 12, bits (3:0) to (0000), then this
device will send a low system reset pulse, on SRESET# (see
byte12, bit7), and changes WD alarm (Byte12, Bit4) status to
“1” then restarts the Watchdog timer again. If the Watchdog
times out a second time, then this device will send another low
pulse on SRESET#, will relatch original hardware strapping
frequency (or second to last software selected frequency, see
byte12, bit6) selection, set WD alarm bit (Byte12, bit4) to ‘1,’
then start WD timer again. The above-described sequence will
keep repeating until the BIOS clears the SMBus byte12 bits
(3:0). Once the BIOS sets Byte 12 bits (3:0) = 0000, then the
Watchdog timer is turned off and the WD alarm bit (Byte 12,
bit4) is reset to ‘0.’
Table 9. Spread Spectrum Table
Mode
SST1
SST0
% Spread
0
0
0
+0.14, –1.23
0
0
1
+0, –1.00
0
1
0
+0, –0.60
0
1
1
+0, –0.52
1
0
0
+0.72, –0.71
1
0
1
+0.47, –0.49
1
1
0
+0.34, –0.33
1
1
1
+0.30, –0.28
Swing Select Functions Through Hardware
MULTSEL
Board Target
Trace/Term Z
Reference R,
IREF = VDD/(3*Rr)
Output Current
VOH@Z
0
50 Ohm
Rr = 221 1%,
IREF = 5.00mA
IOH = 4* Iref
1.0V@50
1
50 Ohm
Rr = 475 1%,
IREF = 2.32mA
IOH = 6* Iref
0.7V@50


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