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FL5150MX Datasheet(PDF) 6 Page - ON Semiconductor |
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FL5150MX Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 23 page © 2016 Fairchild Semiconductor Corporation www.fairchildsemi.com FL5150/60 • 1.0 5 Pin Configuration Figure 7. Pin Assignments Pin Definitions Pin# Name Description 1 ZC Monitor ZC Monitor This signal is used for the zero crossing threshold. 2 DIM Control DIM Control The voltage at this pin is the input for an 8 Bit ADC with a 2.5 V reference. Table 5 shows the pulse width selection per DIM Control pin voltage. This pin sources 10 A of current so that with an external adjustable resistor, the dim pulse width can be selected. With a 4 to 1 resistor divided, a 0 to 10 V DC (Ground reference to pin 5) signal can be used to control the dim pulse width. 3 VDD VDD The internal 5 V supply for the digital logic 4 DIM Mode DIM Mode This pin selects either trailing edge or leading edge pulse width dimming. When a Power-On-Reset (POR) occurs, this pin will be monitored for its logic level. If it is connected to GND then trailing edge dimming will be selected. If it is connected to VDD then leading edge dimming will be selected. The DIM Mode state is latched at startup (60 ms) and will remain in its selected DIM Mode until a POR signal occurs. 5 GND GND Supply input for the FL5150/60 circuitry 6 VS VS Supply input for the FL5150/60 circuitry. An internal shunt regulator will clamp this pin at 17 V. 7 Low Power Low Power When an off state is selected (DIM Control pin at 0 V) an internal PMOS transistor will be enabled which shorts this pin to VS. If an external NPN transistor is used per Figure 2, the FL5150/60 power consumption will be reduced to typically 100 mW. 8 OC Sense2 OC Sense2 An external resistor connected to the collector/drain of Q2 sets the maximum voltage difference across Q1 and Q2 for both positive and negative half cycles. 9 DRV Gate DRV Gate Gate drive signal for external IGBT or MOSFET transistors. 10 OC Sense1 OC Sense1 An external resistor connected to the collector/drain of Q1 sets the maximum voltage difference across Q1 and Q2 for both positive and negative half cycles. 10 GND DIM Control VS ZC Monitor DRV Gate VDD PIN 1 2 1 3 6 7 4 5 OC Sense1 OC Sense2 9 8 DIM Mode Low Power |
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