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SABC161RI-L16M Datasheet(PDF) 18 Page - Siemens Semiconductor Group |
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SABC161RI-L16M Datasheet(HTML) 18 Page - Siemens Semiconductor Group |
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18 / 60 page  Semiconductor Group 18 1998-05-01 C161RI The C161RI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run- time: Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap Priority Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow RESET RESET RESET 00’0000H 00’0000H 00’0000H 00H 00H 00H III III III Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00’0008H 00’0010H 00’0018H 02H 04H 06H II II II Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 00’0028H 00’0028H 00’0028H 00’0028H 00’0028H 0AH 0AH 0AH 0AH 0AH I I I I I Reserved [2CH – 3CH][0BH – 0FH] Software Traps TRAP Instruction Any [00’0000H – 00’01FCH] in steps of 4H Any [00H – 7FH] Current CPU Priority |
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