The Smart Timing Choice



The Smart Timing Choice



SiT3808

1 MHz to 80 MHz High Performance MEMS VCXO

Rev. 1.01

Page 5 of 11

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Timing Diagram

Figure 7. Startup Timing (OE/ST Mode)

Figure 8. Standby Resume Timing (ST Mode Only)

u

Figure 9. OE Enable Timing (OE Mode Only)

Figure 10. OE Disable Timing (OE Mode Only)

Notes:

13. SiT3808 supports “no runt” pulses and “no glitch” output during startup or resume.

14. SiT3808 supports gated output which is accurate within rated frequency stability from the first cycle.

80% Vdd, 2.5/2.8/3.3V devices

80% Vdd, 1.8V devices

Vdd

Pin 4 Voltage

CLK Output

T_start

T_start: Time to start from power-off

No Glitch

during start up

50% Vdd

Vdd

ST Voltage

CLK Output

T_resume

T_resume: Time to resume from ST

50% Vdd

Vdd

OE Voltage

CLK Output

T_oe

T_oe: Time to re-enable the clock output

50% Vdd

Vdd

OE Voltage

CLK Output

T_oe: Time to put the output in High Z mode

HZ

T_oe