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MP8720 Datasheet(PDF) 15 Page - Monolithic Power Systems

Part No. MP8720
Description  26V,10A, High Efficiency, Fast Transient, Synchronous, Buck Converter with adjustable CLM
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8720 Datasheet(HTML) 15 Page - Monolithic Power Systems

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MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
MP8720 Rev. 1.01
www.MonolithicPower.com
15
8/1/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
Table 2: MODE Selection
State
VOUT
DCM/CCM
Resistor to GND
M1
Vo < 3V
DCM
0Ω
M2
Vo < 3V
CCM
90kΩ
M3
Vo ≥ 3V
CCM
150kΩ
M4
Vo ≥ 3V
DCM
>230kΩ or float
Power Good (PG)
The MP8720 uses a power good (PG) output to
indicate whether the output voltage of the VOUT
regulator is ready. PG is the open drain of a
MOSFET. It should be connected to VCC or
another voltage source through a resistor (e.g.:
100kΩ). After the input voltage is applied, the
MOSFET is turned on, so PG is pulled to GND
before SS is ready. After VFB reaches 95% of
VREF, PG is pulled high (after a delay time within
10µs). When VFB drops to 90% of VREF, PG is
pulled low.
Soft Start (SS)
The
MP8720
employs
a
soft-start
(SS)
mechanism to ensure a smooth output during
power-up. When EN becomes high, the internal
reference voltage ramps up gradually, and the
output voltage ramps up smoothly as well.
Once the reference voltage reaches the target
value, the soft start finishes, and the MP8720
enters steady-state operation (see Figure 7).
Figure 7: Start-Up Power Sequence
If the output is pre-biased to a certain voltage
during start-up, the IC disables the switching of
both the high-side and the low-side switches
until the voltage on the internal reference
exceeds the sensed output voltage at the FB
node.
Output Discharge
The MP8720 discharges the output through an
internal 100Ω resistor when the controller is
turned off by a protection function (UVP, OCP,
OVP, UVLO, or thermal shutdown).
Over-Current Limit (OCL)
The MP8720 has cycle-by-cycle over-current
limiting control. The current-limit circuit employs
a valley current-sensing algorithm. The MP8720
uses the RDS(ON) of the LS-FET as a current-
sensing element. If the magnitude of the
current-sense signal is above the current-limit
threshold, the PWM is not allowed to initiate a
new cycle, even if FB is lower than REF (see
Figure 8).
Figure 8: Valley Current-Limit Control
Since the comparison is done during the LS-
FET on state, the over-current trip level sets the
valley level of the inductor current. The
maximum load current at the over-current
threshold (IOC) can be calculated using Equation
(2):
 inductor
OC
I
I
I _ limit
2
(2)
The over-current limit (OCL) limits the inductor
current and does not latch off. In an over-
current condition, the current to the load
exceeds the current to the output capacitor, so
the output voltage tends to fall off. Eventually,
the current ends up crossing the under-voltage
protection (UVP) threshold and latches off.
Fault latching can be reset by EN going low or
cycling the power of VIN.
Current Limit (CLM) Selection
The MP8720 implements an adjustable valley
CLM by connecting CLM to GND with different
resistor values (see Table 3).


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