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PNX1501E Datasheet(PDF) 3 Page - NXP Semiconductors |
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PNX1501E Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 100 page  Philips Semiconductors PNX15xx Series Volume 1 of 1 12NC 9397 750 14321 © Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved. Product data sheet Rev. 2 — 1 December 2004 -3 10.1.2 timestamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 10.1.3 event sequence monitoring and signal generation 2-22 10.1.4 GPIO pin reset value . . . . . . . . . . . . . . . . . . . . . 2-23 10.2 IR Remote Control Receiver and Blaster . . . . 2-23 10.3 PCI-2.2 & XIO-16 Bus Interface Unit . . . . . . . 2-23 10.3.1 PCI Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 10.3.2 Simple Peripheral Capabilities (‘XIO-8/16’) . . 2-24 10.3.3 IDE Drive Interface . . . . . . . . . . . . . . . . . . . . . . . 2-26 10.4 10/100 Ethernet MAC . . . . . . . . . . . . . . . . . . . . . 2-26 11. Endian Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 12. System Debug . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 Chapter 3: System On Chip Resources 1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 2. System Memory Map . . . . . . . . . . . . . . . . . . . . 3-1 2.1 The PCI View . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 2.2 The CPU View. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 2.3 The DCS View Or The System View . . . . . . . . 3-4 2.4 The Programmable DCS Apertures . . . . . . . . . 3-5 2.4.1 DCS DRAM Aperture Control MMIO Registers3-6 2.5 Aperture Boundaries . . . . . . . . . . . . . . . . . . . . . . 3-6 3. System Principles . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1 Module ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2 Powerdown bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3 System Module MMIO registers . . . . . . . . . . . . 3-8 4. System Endian Mode . . . . . . . . . . . . . . . . . . . . 3-8 4.1 System Endian Mode MMIO registers . . . . . . . 3-9 5. System Semaphores . . . . . . . . . . . . . . . . . . . . 3-9 5.1 Semaphore Specification . . . . . . . . . . . . . . . . . . 3-9 5.2 Construction of a 12-bit ID . . . . . . . . . . . . . . . . . 3-9 5.3 The Master Semaphore. . . . . . . . . . . . . . . . . . . 3-10 5.4 Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 5.5 Semaphore MMIO Registers. . . . . . . . . . . . . . . 3-11 6. System Related Information for TM32603-12 6.1 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 6.2 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 6.3 System Parameters for TM3260 . . . . . . . . . . . 3-15 6.3.1 TM3260 System Parameters MMIO Registers .3- 16 7. Video Input and Output Routers . . . . . . . . 3-16 7.1 MMIO Registers for the Input/Output Video/Data Router3-17 8. Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 8.1 Miscellaneous System MMIO registers. . . . . . 3-27 9. System Registers Map Summary . . . . . . . 3-29 10. Simplified Internal Bus Infrastructure . . 3-30 11. MMIO Memory MAP . . . . . . . . . . . . . . . . . . . . . 3-31 12. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Chapter 4: Reset 1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 2. Functional Description . . . . . . . . . . . . . . . . . . 4-1 2.1 RESET_IN_N or POR_IN_N? . . . . . . . . . . . . . . 4-3 2.2 The watchdog Timer . . . . . . . . . . . . . . . . . . . . . . 4-4 2.2.1 The Non Interrupt Mode . . . . . . . . . . . . . . . . . . . 4-4 2.2.2 The Interrupt Mode. . . . . . . . . . . . . . . . . . . . . . . . 4-5 2.3 The Software Reset . . . . . . . . . . . . . . . . . . . . . . . 4-6 2.4 The External Software Reset . . . . . . . . . . . . . . . 4-6 3. Timing Description. . . . . . . . . . . . . . . . . . . . . . . 4-7 3.1 The Hardware Timing . . . . . . . . . . . . . . . . . . . . . . 4-7 3.2 The Software Timing . . . . . . . . . . . . . . . . . . . . . . 4-8 4. Register Definitions . . . . . . . . . . . . . . . . . . . . . . 4-9 5. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Chapter 5: The Clock Module 1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 2. Functional Description . . . . . . . . . . . . . . . . . . 5-1 2.1 The Modules and their Clocks . . . . . . . . . . . . . . 5-4 2.2 Clock Sources for PNX15xx Series. . . . . . . . . . 5-7 2.2.1 PLL Specification . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 2.2.2 The Clock Dividers . . . . . . . . . . . . . . . . . . . . . . . 5-10 2.2.3 The DDS Clocks . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 2.2.4 DDS and PLL Assignment Summary . . . . . . . 5-11 2.2.5 External Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 2.3 Clock Control Logic . . . . . . . . . . . . . . . . . . . . . . 5-13 2.4 Bypass Clock Sources. . . . . . . . . . . . . . . . . . . . 5-14 2.5 Power-up and Reset sequence . . . . . . . . . . . . 5-15 2.6 Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 2.7 Clock Frequency Determination . . . . . . . . . . . 5-16 2.8 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 2.8.1 Wake-Up from Power Down . . . . . . . . . . . . . . . 5-17 2.9 Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 2.10 VDO Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 2.11 GPIO Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 2.11.1 Setting GPIO[14:12]/GCLOCK[2:0] as Clock Outputs5-20 2.11.2 GPIO[6:4]/CLOCK[6:4] as Clock Outputs . . . . 5-20 2.12 Clock Block Diagrams . . . . . . . . . . . . . . . . . . . . 5-20 2.12.1 TM3260, DDR and QVCP clocks . . . . . . . . . . . 5-21 2.12.2 Clock Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 2.12.3 Internal PNX15xx Series Clock from Dividers 5-24 2.12.4 GPIO Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 2.12.5 External Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 2.12.6 SPDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 3. Registers Definition . . . . . . . . . . . . . . . . . . . . . 5-31 3.1 Registers Summary . . . . . . . . . . . . . . . . . . . . . . 5-31 3.2 Registers Description . . . . . . . . . . . . . . . . . . . . . 5-34 |
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