MT90883 datasheet(16/97 Pages) ZARLINK

Part #	MT90883

Description	TDM to Packet Processors

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Manufacturer	ZARLINK [Zarlink Semiconductor Inc]

Direct Link	http://www.zarlink.com

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MT90880/1/2/3

Data Sheet

16

Zarlink Semiconductor Inc.

Table 7 - RMII Interface

3.4

PCI Interface

The PCI signals are NOT 5 V tolerant.

All PCI outputs are high impedance while S_RST is low.

Active low signals are designated by a # suffix, in accordance with the convention used in the PCI specification.

Signal

I/O

Package Balls

Description

ref_clk

I U

AB11

Synchronous clock reference for receive,

transmit and control interface.

Common to both RMII ports.

RMII Port A

rm0_rxd[1:0]

I U

AE9 [1], AD9 [0]

Receive data

rm0_rxdv/ crs

I D

AF7

Carrier sense & receive data valid

rm0_txen

O U

AD6

Transmit enable

rm0_txd[1:0]

O U

AE6 [1], AD7 [0]

Transmit data

RMII Port B

rm1_rxd[1:0]

I U

AE13 [1], AF13 [0]

Receive data

rm1_rxdv/ crs

I D

AE12

Carrier sense & receive data valid

rm1_txen

O U

AD10

Transmit enable

rm1_txd[1:0]

O U

AF10 [1], AD11 [0]

Transmit data

Signal

I/O

Package Balls

Description

pci_clk

I

AF20

PCI clock

pci_rst#

I

AE19

PCI reset

pci_req#

O

AC19

PCI request

pci_gnt#

I

AD19

PCI grant

pci_ad[31:0]

I O

AE20 [31], AB19 [30], AF21 [29], AC20 [28],

AD20 [27], AE21 [26], AF22 [25], AD21 [24],

AF23 [23], AD22 [22], AE23 [21], AC21 [20],

AE24 [19], AC22 [18], AD24 [17], AC23 [16],

AC26 [15], AB25 [14], W23 [13], AA24 [12],

AB26 [11], AA25 [10], Y24 [9], AA26 [8],

V24 [7], U23 [6], V25 [5], T23 [4] T24 [3],

R23 [2], T25 [1], T26 [0]

PCI address / data

pci_cbe[3:0]#

I O

AE22 [3], AB23 [2], Y23 [1], W24 [0]

PCI control / byte enable

pci_par

I O

AC25

PCI parity

pci_frame#

I O

AE25

PCI frame

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