1

LTC4301L

4301lf

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

Hot Swappable 2-Wire

Bus Buffer with Low Voltage

Level Translation

s

Level Translates 1V Signals to Standard 3.3V and

5V Logic Rails

s

Allows Bus Pull-Up Voltages as Low as 1V on

SDAIN and SCLIN

s

Bidirectional Buffer* for SDA and SCL Lines

Increases Fanout

s

Prevents SDA and SCL Corruption During Live Board

Insertion and Removal from Backplane

s

Isolates Input SDA and SCL Line from Output

s

10kV Human Body Model ESD Protection

s

Supports Clock Stretching, Arbitration and

Synchronization

s

s

CS Gates Connection from Input to Output

s

Standards (Up to 400kHz Operation)

s

Small 8-Pin MSOP and DFN (3mm

× 3mm) Packages

s

Hot Board Insertion

s

Servers

s

Capacitance Buffer/Bus Extender

s

Desktop Computers

, LTC and LT are registered trademarks of Linear Technology Corporation.

The LTC

I/O card insertion into a live backplane without corruption

of the data and clock busses. In addition, the LTC4301L

SDAIN and SCLIN pins are compatible with systems with

pull-up voltages as low as 1V. Control circuitry prevents

the backplane from being connected to the card until a

stop bit or a bus idle is present. When the connection is

made, the LTC4301L provides bidirectional buffering,

keeping the backplane and card capacitances isolated.

When driven low, the CS input pin allows the part to

connect after a stop bit or bus idle occurs. Driving CS high

breaks the connection between SCLIN and SCLOUT and

between SDAIN and SDAOUT. A logic high on READY

indicates that the backplane and card sides are connected

together.

The LTC4301L is offered in 8-pin DFN (3mm

× 3mm) and

MSOP packages.

Input-Output Connection

OUTPUT

SIDE

20pF

INPUT

SIDE

55pF

4301 TA01b

1

µs/DIV

0.5V/DIV

µP

SDA

SCL

GND

SDAIN

SCLIN

CS

SDAOUT

SCLOUT

READY

LTC4301L

GND

2k

10k

2k

10k

0.01

µF

SDA

SCL

1.2V

3.3V

4301l TA01a

*Patent Pending