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IDT70V05L20PFI Datasheet(PDF) 11 Page - Integrated Device Technology

Part No. IDT70V05L20PFI
Description  HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
Download  22 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT70V05L20PFI Datasheet(HTML) 11 Page - Integrated Device Technology

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6.42
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
11
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)
NOTES:
1. R/
W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW
CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of
CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last,
CE, or R/W.
7. Timing depends on which enable signal is de-asserted first,
CE, or R/W.
8. If
OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If
OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM,
CE = VIL and SEM = VIN. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)
2941 drw 09
tWC
tAS
tWR
tDW
tDH
ADDRESS
DATAIN
CE or SEM
R/
W
tAW
tEW
(3)
(2)
(6)
(9)
R/
W
tWC
tHZ
tAW
tWR
tAS
tWP
DATAOUT
(2)
tWZ
tDW
tDH
tOW
OE
ADDRESS
DATAIN
CE
(6)
(4)
(4)
(3)
2941 drw 08
(7)
(7)
or
SEM
(9)


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