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IDT70V05L20PFI Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT70V05L20PFI
Description  HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT70V05L20PFI Datasheet(HTML) 1 Page - Integrated Device Technology

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©2000 Integrated Device Technology, Inc.
MARCH 2000
DSC 2941/6
1
IDT70V05S/L
HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
Features
x
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
x
x
x
x
x
High-speed access
Commercial: 15/20/25/35/55ns (max.)
Industrial: 20/25/35/55ns (max.)
x
x
x
x
x
Low-power operation
IDT70V05S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
IDT70V05L
Active: 380mW (typ.)
Standby: 660
µW (typ.)
x
x
x
x
x
IDT70V05 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
x
x
x
x
x
M/
S = VIH for BUSY output flag on Master
M/
S = VIL for BUSY input on Slave
x
x
x
x
x
Interrupt Flag
x
x
x
x
x
On-chip port arbitration logic
x
x
x
x
x
Full on-chip hardware support of semaphore signaling
between ports
x
x
x
x
x
Fully asynchronous operation from either port
x
x
x
x
x
TTL-compatible, single 3.3V (±0.3V) power supply
x
x
x
x
x
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
x
x
x
x
x
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
NOTES:
1. (MASTER):
BUSY is output; (SLAVE): BUSY is input.
2.
BUSY outputs and INT outputs are non-tri-stated push-pull.
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
WL
CEL
OEL
BUSYL
A12L
A0L
2941 drw 01
I/O0L-I/O7L
CEL
OEL
R/
WL
SEML
INTL
M/
S
BUSYR
I/O0R-I/O7R
A12R
A0R
SEMR
INTR
CER
OER
(2)
(1,2)
(1,2)
(2)
R/
WR
CER
OER
13
13
R/WR


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