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IDT70V05L20PFI Datasheet(PDF) 8 Page - Integrated Device Technology

Part No. IDT70V05L20PFI
Description  HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT70V05L20PFI Datasheet(HTML) 8 Page - Integrated Device Technology

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6.42
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
8
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2.
This parameter is determined by device characterization but is not production tested.
3. To access SRAM,
CE = VIL, SEM = VIH.
4. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70V05X15
Com'l Only
70V05X20
Com'l
& Ind
70V05X25
Com'l
& Ind
Unit
Symbol
Parameter
Min.Max.Min.
Max.Min.
Max.
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
25
____
ns
tAA
Address Access Time
____
15
____
20
____
25
ns
tACE
Chip Enable Access Time
(3)
____
15
____
20
____
25
ns
tAOE
Output Enable Access Time(3)
____
10
____
12
____
13
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time(1,2)
3
____
3
____
3
____
ns
tHZ
Output High-Z Time
(1,2)
____
10
____
12
____
15
ns
tPU
Chip Enable to Power Up Time
(1,2)
0
____
0
____
0
____
ns
tPD
Chip Disable to Power Down Time
(1,2)
____
15
____
20
____
25
ns
tSOP
Semaphore Flag Update Pulse (
OE or SEM)10
____
10
____
10
____
ns
tSAA
Semaphore Address Access
(3)
____
15
____
20
____
25
ns
2941 tbl 11a
70V05X35
Com'l
& Ind
70V05X55
Com'l
& Ind
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
35
____
55
____
ns
tAA
Address Access Time
____
35
____
55
ns
tACE
Chip Enable Access Time(3)
____
35
____
55
ns
tAOE
Output Enable Access Time
(3)
____
20
____
30
ns
tOH
Output Hold from Address Change
3
____
3
____
ns
tLZ
Output Low-Z Time
(1,2)
3
____
3
____
ns
tHZ
Output High-Z Time
(1,2)
____
15
____
25
ns
tPU
Chip Enable to Power Up Time
(1,2)
0
____
0
____
ns
tPD
Chip Disable to Power Down Time
(1,2)
____
35
____
50
ns
tSOP
Semaphore Flag Update Pulse (
OE or SEM)15
____
15
____
ns
tSAA
Semaphore Address Access
(3)
____
35
____
55
ns
2941 tbl 11b


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