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LR8501 Datasheet(PDF) 7 Page - Leshan Radio Company

Part No. LR8501
Description  1.5MHz 600mA Synchronous Step-Down Converter with Low Quiescent Current
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Maker  LRC [Leshan Radio Company]
Homepage  http://www.lrc.cn/
Logo LRC - Leshan Radio Company

LR8501 Datasheet(HTML) 7 Page - Leshan Radio Company

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The LR8501 uses a constant frequency,
current mode step-down architecture. Both the
main (P-channel MOSFET) and synchronous
(N-channel MOSFET) switches are internal.
During normal operation, the internal top power
MOSFET is turned on each cycle when the
oscillator sets the RS latch, and turned off when
the current comparator, ICOMP, resets the RS latch.
The peak inductor current at which ICOMP resets
the RS latch, is controlled by the output of error
amplifier EA. When the load current increases, it
causes a slight decrease in the feedback voltage,
FB, relative to the 0.6V reference, which in turn,
causes the EA amplifier’s output voltage to
increase until the average inductor current
matches the new load current. While the top
MOSFET is off, the bottom MOSFET is turned on
until either the inductor current starts to reverse,
as indicated by the current reversal comparator
IRCMP, or the beginning of the next clock cycle.
The LR8501 will operate with input voltage as
low as 1.8V, however, the maximum load current
decreases at lower input due to large IR drop on
the main switch and synchronous rectifier. The
slope compensation signal reduces the peak
inductor current as a function of the duty cycle to
prevent sub-harmonic oscillations at duty cycles
greater than 50%.Conversely the current limit
increase as the duty cycle decreases.
At light loads, the inductor current may reach
zero reverse on each pulse. The bottom MOSFET
is turned off by the current reversal comparator,
IRCMP, and the switch voltage will ring. This is
discontinuous mode operation, and is normal
behavior for the switching regulator. At very light
loads, the LR8501 will automatically skip pulses in
discontinuous mode operation to maintain output
Slope compensation provides stability in
constant frequency architecture by preventing
sub-harmonic oscillations at high duty cycles. It is
compensating ramp to the inductor current signal
at duty cycles in excess of 50%. This slope
compensated current mode PWM control provides
stable switching and cycle-by-cycle current limit
for excellent load and line response.
At very light loads, the chip automatically
enters power saving mode. In power saving mode
at light load, a control circuit puts most of the
circuit into sleep in order to reduce quiescent
current and improve efficiency at light load. When
the output voltage drops to certain threshold, the
control circuit turns back on the oscillator and the
PWM control loop, boosting output backup. When
an upper threshold is reached, the control circuit
again puts most of circuit into sleep, reducing
quiescent current. During power saving mode
operation, the converter positions the output
voltage slightly higher than the nominal output
voltage during PWM operation, allowing additional
headroom for voltage drop during a load transient
from light to heavy load. While the power saving
mode improves light load efficiency, however, with
the turning on and off, the noise or ripple voltage is

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