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5962R9858302VXXA Datasheet(PDF) 3 Page - Aeroflex Circuit Technology |
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5962R9858302VXXA Datasheet(HTML) 3 Page - Aeroflex Circuit Technology |
3 / 10 page 3 1.1 Hardware Interface 1.1.1 Interfacing with External Memory The UT80CRH196KD can interface with a variety of external memory devices. It supports either a fixed 8-bit bus width or a dynamic 8-bit/16-bit bus width, internal READY control for slow external memory devices, a bus-hold protocol that enables external devices to take over the bus, and several bus-control modes. These features provide a great deal of flexibility when interfacing with external memory devices. 1.1.1.1 Chip Configuration Register The Chip Configuration Register (CCR) is used to initialize the UT80CRH196KD immediately after reset. The CCR is fetched from external address 2018H (Chip Configuration Byte) after removal of the reset signal. The Chip Configuration Byte (CCB) is read as either an 8-bit or 16-bit word depending on the value of the BUSWIDTH pin. The composition of the bits in the CCR are shown in Table 4. There are 8 configuration bits available in the CCR. However, bits 7 and 6 are not used by the UT80CRH196KD. Bits 5 and 4 comprise the READY mode control which define internal limits for waitstates generated by the READY pin. Bit 3 controls the definition of the ALE/ADV pin for system memory controls while bit 2 selects between the different write modes. Bit 1 selects whether the UT80CRH196KD will use a dynamic 16- bit bus or whether it will be locked in as an 8-bit bus. Finally, Bit 0 enables the Power Down mode and allows the user to disable this mode for protection against inadvertent power downs. 1.1.1.2 Bus Width and Memory Configurations The UT80CRH196KD external bus can operate as either an 8- bit or 16-bit multiplexed address/data bus (see figure 2). The value of bit 1 in the CCR determines the bus operation. A logic low value on CCR.1 locks the bus controller in 8-bit bus mode. If, however, CCR.1 is a logic high, then the BUSWIDTH signal is used to decide the width of the bus. The bus is 16 bits wide when the BUSWIDTH signal is high, and is 8 bits when the BUSWIDTH signal is low. 1.1.2 Reset To reset the UT80CRH196KD, hold the RESET pin low for at least 16 state times after the power supply is within tolerance and the oscillator has stabilized. Resets following the power-up reset may be asserted for at least one state time, and the device will turn on a pull-down transistor for 16 state times. This enables the RESET signal to function as the system reset. The reset state of the external I/O is shown in Table 9, and the register reset values are shown in Table 8. 1.1.3 Instruction Set The instruction set for the UT80CRH196KD is compatible with the industry standard MCS-96 instruction set used on the 8XC196KD. Notes: 1.The first instruction read following reset will be from location 2080h. All other external memory can be used as instruction a nd/or data memory. Table 4. Chip Configuration Register Bit Function 7 N/A 6 N/A 5 IRC1 - Internal READY Mode Control 4 IRC0 - Internal READY Mode Control 3 Address Valid Strobe Select (ALE/ADV) 2 Write Strobe Mode Select (WR and BHE/WRL and WRH) 1 Dynamic Bus Width Enable 0 Enable Power Down Mode Table 5. Memory Map Memory Description Begin End External Memory1 02080H 0FFFFH Reserved 0205EH 0207FH PTS Vectors 02040H 0205DH Upper Interrupt Vectors 02030H 0203FH Reserved 02020H 0202FH Reserved 02019H 0201FH Chip Configuration Byte 02018H 02018H Reserved 02014H 02017H Lower Interrupt Vectors 02000H 02013H External Memory 00400H 1FFFH Internal Memory (RAM) 0001AH 003FFH Special Function Registers 00000H 00019H |
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