U62256AS2A10 datasheet(1/10 Pages) ZMD

Part #	U62256AS2A10

Description	STANDARD 32K X 8 SRAM

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Manufacturer	ZMD [Zentrum Mikroelektronik Dresden AG]

Direct Link	http://www.zmdi.com

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U62256A

April 20, 2004

11

!

32768x8 bit static CMOS RAM

!

Access times 70 ns, 100 ns

!

Common data inputs and

data outputs

!

Three-state outputs

!

Typ. operating supply current

70 ns: 50 mA

100 ns: 40 mA

!

TTL/CMOS-compatible

!

Automatical reduction of power

dissipation in long Read Cycles

!

Power supply voltage 5 V + 10 %

!

Operating temperature ranges

0 to 70 °C

-40 to 85 °C

-40 to 125 °C

!

QS 9000 Quality Standard

!

ESD protection > 2000 V

(MIL STD 883C M3015.7)

!

Latch-up immunity >100 mA

!

Packages: PDIP28 (600 mil)

SOP28 (330 mil)

Standard 32K x 8 SRAM

Features

The U62256A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Read

- Standby

- Write

- Data Retention

The memory array is based on a

6-transistor cell.

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word read will be available at

the outputs DQ0-DQ7. After the

address change, the data outputs

go High-Z until the new information

read is available. The data outputs

have not preferred state.

The Read cycle is finished by the

falling edge of W, or by the rising

edge of E, respectively.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

Description

Pin Configuration

1

A14

VCC

28

2

A12

W

27

4

A6

A8

25

5

A5

A9

24

3

A7

A13

26

6

A4

A11

23

7

A3

G

22

8

A2

A10

21

12

DQ1

DQ5

17

9

A1

E

20

10

A0

DQ7

19

11

DQ0

DQ6

18

13

DQ2

DQ4

16

14

VSS

DQ3

15

Top View

Signal Name

Signal Description

A0 - A14

Address Inputs

DQ0 - DQ7

Data In/Out

E

Chip Enable

G

Output Enable

W

Write Enable

VCC

Power Supply Voltage

VSS

Ground

Pin Description

PDIP

SOP

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