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SPI-SP10T-63

Table 1: Switch Logic Table

A0

A1

A2

A3

Switch State

1

0

1

0

Com<->J1

1

0

1

1

Com<->J2

1

0

0

1

Com<->J3

1

0

0

0

Com<->J4

1

1

N.C.

N.C.

Com<->J5

0

1

N.C.

N.C.

Com<->J6

0

0

1

0

Com<->J7

0

0

1

1

Com<->J8

0

0

0

1

Com<->J9

0

0

0

0

Com<->J10

The SPI-SP10T-63 serial interface consists of 4 control bits per unit that select the desired switch state, as shown

in Table 1: Switch Logic Table.

The serial interface is a 4-bit serial in, parallel-out shift register buffered by a transparent latch.

It is controlled by three-wire SPI protocol using Data, Clock, and Latch Enable (LE) and an additional Lock for

added noise immunity and increased exibility in controlling the units. All signal voltages are compatible with TTL

and LVTTL. The Data and Clock inputs allow data to be serially entered into the shift register, a process that is

independent of the state of the LE input.

The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift reg-

ister control the switch. When LE is brought LOW, data in the shift register is latched.

Lock is used to lock the current state of the switch regardless of LE state or shift register, while allowing the LE to

pass to other switches in the chain. If Lock is at logic HIGH the switch will respond to LE normally, when Lock is at

logic LOW the switch will not respond to LE. If Lock is not required it can be kept constantly at logic high.

The shift register should be loaded while LE is held LOW to prevent the switch state from changing as data is en-

tered. If multiple units are connected in series, data for all units should be entered before raising the LE to prevent

switches assuming unanticipated states. Thus for example if three units are connected in daisy chain all 12 bits of

control should be entered before raising the LE(see figures 2-4 for connecting units in daisy chain).

The LE input should then be toggled HIGH and brought LOW again, latching the new data. The timing for this

operation is defined by Figure 1: Serial Interface Timing Diagram and Table 2: Serial Interface AC Characteristics.

Note:

1. LE is connected in parallel to all units in a daisy chain using the switches internal buffers to prevent control current from increasing as more

units are connected.

2. Mini-Circuits’ SPI converter, model RS232/USB-SPI, can be used to provide a single USB or RS232 interface for up to 50 daisy-chained

SPI-SP10T-63 switches, with full software support (optional accessories on page 11).

Control Interface

Figure 1: Serial Interface Timing Diagram

LE

Clock

Data

A0

t

LESUP

t

SDSUP

t

LLEPW

t

SDHLD

A1

A2

A3

Table 2. Serial Interface AC Characteristics

Symbol

Parameter

Min.

Max.

Units

Serial data clock frequency

20

MHz

Serial clock HIGH time

8

ns

Serial clock LOW time

14

ns

8

ns

8

ns

Serial data set-up time before clock rising

edge

8

ns

Serial data hold time after clock falling

edge

1

ns