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N8815A-1FP Datasheet(PDF) 10 Page - Keysight Technologies |
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N8815A-1FP Datasheet(HTML) 10 Page - Keysight Technologies |
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10 / 47 page  10 | Keysight | Infiniium V-Series Oscilloscopes - Data Sheet Industry’s Fastest Mixed Signal Oscilloscope World’s fastest 20 GSa/s digital channels, delivering best analog and digital performance Today’s designs require access to complex triggers and multiple instruments� A mixed signal oscilloscope (MSO) integrates traditional analog channels with 16 digital channels, providing up to 20 channels you can use at once� Keysight MSOs seamlessly integrate the familiar controls of an oscilloscope with the additional digital data acquisition and pattern recognition of a logic analyzer� You can trigger across any combination of analog and digital channels, as well as decode the acquired data� The MSO has the ability to label each individual channel as part of a bus for decoding, saving hours of manual work� With the fastest 20 GSa/s sample rate, it provides superior insight into low-speed serial and high-speed parallel bus interfaces� MSO optimized for DDR/LPDDR2, 3, and 4 protocol triggering and decode The MSO is specially targeted at DDR/LPDDR2, 3 and 4 memory technologies, simplifying the complicated task of triggering, analyzing and debugging the parallel buses� The additional digital channels mean you can probe at the various command signals to easily trigger on the different DDR commands such as read, write, activate, precharge and more� DDR triggering makes read and write separation easy, providing fast electrical characterization, real-time eye analysis and timing measurements� The DDR protocol decoder can decipher the DDR packets and provide a time-aligned listing window to search for specific packet information� All of the above features come standard with the MSO� The MSO is fully compatible with Keysight’s 90-pin logic analysis connectors, making it easy to connect to your devices� DDR3 test setup with mixed signal oscilloscope� DDR3 protocol decode and write command trigger� DDR3 write data burst eye-diagram analysis� |
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