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PALCE26V12 Datasheet(PDF) 4 Page - Advanced Micro Devices |
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PALCE26V12 Datasheet(HTML) 4 Page - Advanced Micro Devices |
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4 / 21 page  AMD 2–309 PALCE26V12 Family FUNCTIONAL DESCRIPTION The PALCE26V12 has fourteen dedicated input lines, two of which can be used as clock inputs. Unused inputs should be tied directly to ground or VCC. Buffers for device inputs and feedbacks have both true and complementary outputs to provide user-selectable signal polarity. The inputs drive a programmable AND logic array, which feeds a fixed OR logic array. The OR gates feed the twelve I/O macrocells (see Figure 1). The macrocell allows one of eight potential output configurations; registered or combinatorial, ac- tive high or active low, with register or I/O pin feedback (see Figure 2). In addition, registered configurations can be clocked by either of the two clock inputs. The configuration choice is made according to the user’s design specification and corresponding program- ming of the configuration bits S0–S3 (see Table 1). Multiplexer controls initially float to VCC (1) through a programmable cell, selecting the “1” path through the multiplexer. Programming the cell connects the control line to GND (0), selecting the “0” path. Table 1. Macrocell Configuration Table S3 S1 S0 Output Configuration 1 0 0 Registered Output and Feedback, Active Low 1 0 1 Registered Output and Feedback, Active High 1 1 0 Combinatorial I/O, Active Low 1 1 1 Combinatorial I/O, Active High 0 0 0 Registered I/O, Active Low 0 0 1 Registered I/O, Active High 0 1 0 Combinatorial Output, Registered Feedback, Active Low 0 1 1 Combinatorial Output, Registered Feedback, Active High S2 Clock Input 1 CLK1/I0 0 CLK2/I3 1 = Unprogrammed EE bit 0 = Programmed EE bit 16072E-4 * D AR Q Q SP AR P1 Pn 0 1 10 11 00 01 OE SP 1 0 0 S 3 S 1 S 2 S CLK2 CLK 1 n = 8,8,10,12,14,16 When S = 1 (unprogrammed) the feedback is selected by S . When S = 0 (programmed), the feedback is the opposite of that selected by S . * 3 3 1 1 Figure 1. PALCE26V12 Macrocell Registered or Combinatorial Each macrocell of the PALCE26V12 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH edge of the selected clock input. Any macrocell can be configured as combinatorial by selecting a multiplexer path that bypasses the flip-flop. Bypass is controlled by bit S1. Programmable Clock The clock input for any flip-flop can be selected to be from either pin 1 or pin 4. A 2:1 multiplexer controlled by bit S2 determines the clock input. Programmable Feedback A 2:1 multiplexer allows the user to determine whether the macrocell feedback comes from the flip-flop or from the I/O pin, independent of whether the output is registered or combinatorial. Thus, registered outputs may have internal register feedback for higher speed (fMAX internal), or I/O feedback for use of the pin as a direct input (fMAX external). Combinatorial outputs may have I/O feedback, either for use of the signal in other equations or for use as another direct input, or register feedback. |
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