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NT5SV8M8DT-6K Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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NT5SV8M8DT-6K Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
3 / 21 page NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM REV 1.1 10/01 3 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. Pin Description CK Clock Input DQ0-DQ15 Data Input/Output CKE Clock Enable DQM, LDQM, UDQM Data Mask CS Chip Select VDD Power (+3.3V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe VDDQ Power for DQs (+3.3V) WE Write Enable VSSQ Ground for DQs BS1, BS0 Bank Select NC No Connection A0 - A11 Address Inputs — — Input/Output Functional Description Symbol Type Polarity Function CLK Input Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. CKE Input Active High Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE Input Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. BS0, BS1 Input — Selects which bank is to be active. A0 - A11 Input — During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, auto- precharge is disabled. During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BS0 and BS1 are used to define which bank to precharge. DQ0 - DQ15 Input- Output — Data Input/Output pins operate in the same manner as on conventional DRAMs. DQM LDQM UDQM Input Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. VDD, VSS Supply — Power and ground for the input buffers and the core logic. VDDQ VSSQ Supply — Isolated power supply and ground for the output buffers to provide improved noise immunity. |
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