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ISPGAL22V10C-15LJ Datasheet(PDF) 9 Page - Lattice Semiconductor |
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ISPGAL22V10C-15LJ Datasheet(HTML) 9 Page - Lattice Semiconductor |
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9 / 15 page  Specifications ispGAL22V10 9 Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See Figure 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition R1 R2 CL A 300 Ω 390 Ω 50pF B Active High ∞ 390 Ω 50pF Active Low 300 Ω 390 Ω 50pF C Active High ∞ 390 Ω 5pF Active Low 300 Ω 390 Ω 5pF SWITCHING TEST CONDITIONS fmax with Internal Feedback 1/(tsu+tcf) Note: tcf is a calculated value, derived by sub- tracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combi- natorial output is equal to tcf + tpd. fmax with No Feedback Note: fmax with no feedback may be less than 1/twh + twl. This is to allow for a clock duty cycle of other than 50%. fmax DESCRIPTIONS R E GI ST ER L OGIC AR R A Y tco tsu CL K Note: fmax with external feedback is cal- culated from measured tsu and tco. fmax with External Feedback 1/(tsu+tco) TEST POINT C * L FROM OUTPUT (O/Q) UNDER TEST +5V *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE R2 R1 CLK REGISTER LOGIC ARRAY tcf tpd REGISTER LOGIC ARRAY CLK tsu + th |
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