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HFA3842 Datasheet(PDF) 17 Page - Intersil Corporation

Part No. HFA3842
Description  Wireless LAN Medium Access Controller
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HFA3842 Datasheet(HTML) 17 Page - Intersil Corporation

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17
• Note: All register cycles, including hardware registers,
incur a short wait state on the PC Card bus to ensure the
host cycle is synchronized with the HFA3842's internal
MCLK.
MEMORY MAPPED REGISTERS IN DATA RAM (MM)
• 1 to 1 correspondence.
• Requires memory arbitration, since registers are actually
locations in HFA3842 memory.
• Attribute memory access is mapped into RAM as Base-
address + 0x400.
• AUX port provides host access to any location in HFA3842
RAM (reserved).
BUFFER ACCESS PATH (BAP)
• No 1 to 1 correspondence between register address and
memory address (due to indirect access through buffer
address pointer registers).
• Auto increment of pointer registers after each access.
• Require memory arbitration since buffers are located in
HFA3842 memory.
• Buffer access may incur additional delay for Hardware
Buffer Chaining.
Buffer Access Paths
The HFA3842 has two independent buffer access paths,
which permits concurrent read and write transfers. The
firmware provides dynamic memory allocation between
Transmit and Receive, allowing efficient memory utilization.
On-the-fly allocation of (128-byte) memory blocks as needed
for reception wastes minimal space when receiving
fragments. The HFA3842 hides management of free
memory from the driver, and allows fast response and
minimum data copying for low latency. The firmware
provides direct access to TX and RX buffers based on
Frame ID (FID). This facilitates Power Management queuing,
and allows dynamic fragmentation and defragmentation by
controller. Simple Allocate /Deallocate commands ensure
low host CPU overhead for memory management.
Hardware buffer chaining provides high performance while
reading and writing buffers. Data is transferred between the
host driver and the HFA3842 by writing or reading a single
register location (The Buffer Access Path, or BAP). Each
access increments the address in the buffer memory. Internally,
the firmware allocates blocks of memory as needed to provide
the requested buffer size. These blocks may not be contiguous,
but the firmware builds a linked list of pointers between them.
When the host driver is transferring data through a buffer
access path and reaches the end of a physical memory block,
hardware in the host interface follows the linked list so that the
buffer access path points to the beginning of the next memory
block. This process is completely transparent to the host driver,
which simply writes or reads all buffer data to the same register.
If the host driver attempts to access beyond the end of the
allocated buffer, subsequent writes are ignored, and reads will
be undefined.
PHY Interface
The HFA3842 is intended to support the PRISM family of
Baseband processors with no additional components. This
family currently includes the HFA3860B, HFA3861B, HFA3861
and HFA3863 baseband processors and the other ICs in the
PRISM radio chip set. (Other baseband processors may be
supported with custom firmware. See your sales representative
for more information). The HFA3842 interfaces to the HFA386X
baseband processors through two serial interfaces. The
Modem Management Interface (MMI) is used to read and write
internal registers in the baseband processor and access per-
packet PLCP information. The Modem Data Interface (MDI)
provides the receive and transmit data paths which transfer the
actual MPDU data.
Serial Control Port (MMI)
The HFA3842 has a serial port that is used to program the
baseband processor. There are individual chip selects and
shared clock and data lines.
The MMI is used to program the registers and functionality of
the PHY baseband processor.
TABLE 6. MEMORY MAPPED REGISTER
I/O OFFSET
NAME
TYPE
00
Command
MM
02
Param0
MM
04
Param1
MM
06
Param2
MM
08
Status
MM
0A
Resp0
MM
0C
Resp1
MM
0E
Resp2
MM
10
InfoFID
MM
20
RxFID
MM
22
AllocFID
MM
24
TxComplFID
MM
18
BAP Select0
MM
1C
BAP Offset0
MM
36
BAP Data0
BAP
1A
BAP Select1
MM
1E
BAP Offset1
MM
38
BAP Data1
BAP
30
EvStat
HW
32
IntEn
HW
34
EvAck
HW
14
Control
MM
28
SwSupport0
MM
2A
SwSupport1
MM
2C
SwSupport2
MM
3A
AuxBase
HW
3C
AuxOffset
HW
3E
AuxData
(Reserved)
HFA3842


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