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HFA3842 Datasheet(PDF) 16 Page - Intersil Corporation

Part No. HFA3842
Description  Wireless LAN Medium Access Controller
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HFA3842 Datasheet(HTML) 16 Page - Intersil Corporation

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HD[15:0]
The host interface is primarily designed for word accesses,
although all byte access modes are fully supported. See
HCE1-, HCE2- for a further description. Note that attribute
memory is specified for and operates with even bytes
accesses only.
HCE1-, HCE2-
The PC Card cycle type and width are controlled with the CE
signals. Word and Byte wide accesses are supported, using
the combinations of HCE1-, HCE2-, and HA0 as specified in
the PC Card standard.
HWE-, HOE-
HOE- and HWE- are only used to access attribute memory.
Common Memory, as specified in the PC Card standard, is
not used in the HFA3842. HOE- is the strobe that enables an
attribute memory read cycle. HWE- is the corresponding
strobe for the attribute memory write cycle. The attribute
space contains the Card Information Structure (CIS) as well
as the Function Configuration Registers (FCR).
HIORD-, HIOWR-
HIORD- and HIOWR- are the enabling strobes for register
access cycles to the HFA3842. These cycles can only be
performed once the initialization procedure is complete and
the HFA3842 has been put into IO mode.
HREG-
This signal must be asserted for I/O or attribute cycles. A
cycle with HREG- unasserted will be ignored as the
HFA3842 does not support common memory.
HINPACK-
This signal is asserted by the HFA3842 whenever a valid I/O
read cycle takes place. A valid cycle is when HCE1-, HCE2-,
HREG-, and HIORD- are asserted, once the initialization
procedure is complete.
HWAIT-
Wait states are inserted in accesses using HWAIT-. The host
interface synchronizes all PC Card cycles to the internal
HFA3842 clock. The following wait states should be
expected:
Direct Read or Write to Hardware Register
• 1/2 to 1 MCLK assertion of HWAIT- for internal
synchronization.
Write to Memory Mapped Register, Buffer Access Path,
or Attribute Space (Post-Write)
• The data required for the write cycle will be latched and
therefore only the synchronizing wait state will occur.
• Until the queued cycle has actually written to the memory,
any subsequent access by the Host will result in a WAIT.
Read to Attribute Space and Memory Mapped Registers
• WAIT will assert until the memory arbitration and access
have completed.
Buffer Access Paths, BAP0 and BAP1
• An internal Pre-Read cycle to memory is initiated by a
host Buffer Read cycle, after the internal address pointer
has auto-incremented. If the next host cycle is a read to
the same buffer, the data will be available without a
memory arbitration delay.
• A single register holds the pre-read data. Thus, any read
access to any other memory-mapped register (or the other
buffer access path) will result in the pre-read data
becoming invalidated.
• If another read cycle has invalidated the pre-read, then a
memory arbitration delay will occur on the next buffer
access path read cycle.
HIREQ-
Immediately after reset, the HIREQ- signal serves as the
RDY/BSY (per the PC Card standard). Once the HFA3842
firmware initialization procedure is complete, HIREQ- is
configured to operate as the interrupt to the PC Card socket
controller. Both Level Mode and Pulse Mode interrupts are
supported. By default, Level mode interrupts are used, so
the interrupt source must be specifically acknowledged or
disabled before the interrupt will be removed.
HRESET
When reset is removed, the CIS table is initialized and, once
complete, HIREQ- is set high (HIREQ- acts as RDY/BSY
from reset and is set high to indicate the card is ready for
use). The CIS table resides in Flash memory and is copied
to RAM during firmware initialization. The host system can
then initialize the card by reading the CIS information and
writing to the configuration register.
ISA PnP
The HFA3842 can be connected to the ISA bus and operate
in a Plug and Play environment with an additional chip such
as the Fujitsu MB86703, Texas Instruments TL16PNP200A,
or Fairchild Semiconductor NM95MS15. See the Application
Note AN9874, “ISA Plug and Play with the HFA3841” for
more details.
Register Interface
The logical view of the HFA3842 from the host is a block of
32 word wide registers. These appear in IO space starting at
the base address determined by the socket controller. There
are three types of registers.
HARDWARE REGISTERS (HW)
• 1 to 1 correspondence between addresses and registers.
• No memory arbitration delay, data transfer directly to/from
registers.
• AUX base and offset are write-only, to set up access
through AUX data port.
HFA3842


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