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HFA3842 Datasheet(PDF) 7 Page - Intersil Corporation

Part No. HFA3842
Description  Wireless LAN Medium Access Controller
Download  26 Pages
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HFA3842 Datasheet(HTML) 7 Page - Intersil Corporation

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7
SYSTEM INTERFACE - PC CARD IO READ 16
Data Delay After HIORD-
tDIORD
--
100
ns
Data Hold Following HIORD-
tHIORD
0-
-
ns
HIORD- Width Time
tWIORD
165
-
-
ns
Address Setup Before HIORD-
tSUA
70
-
-
ns
Address Hold Following HIORD-
tHA
20
-
-
ns
HCE(1, 2)- Setup Before HIORD-
tSUCE
5-
-
ns
HCE(1, 2)- Hold After HIORD-
tHCE
20
-
-
ns
HREG- Setup Before HIORD-
tSUREG
5-
-
ns
HREG- Hold Following HIORD-
tHREG
0-
-
ns
HINPACK- Delay Falling from HIORD-
tDFINPACK
0
-
45
ns
HINPACK- Delay Rising from HIORD-
dDRINPACK
30
-
45
ns
Data Delay from HWAIT- Rising
tDRWT
--
0
ns
HWAIT- Width Time
tWWT
-
-
12,000
ns
SYSTEM INTERFACE - PC CARD IO WRITE 16
Data Setup Before HIORD-
tSUIOWR
30
-
92
ns
Data Hold Following HIORD-
tHIOWR
20
-
-
ns
HIOWR- Width Time
tWIOWR
165
-
-
ns
Address Setup Before HIORD-
tSUA
70
-
-
ns
Address Hold Following HIORD-
tHA
20
-
-
ns
HCE(1, 2)- Setup Before HIORD-
tSUCE
5-
-
ns
HCE(1, 2)- Hold Following HIORD-
tHCE
20
-
-
ns
HREG- Setup Before HIORD-
tSUREG
5-
-
ns
HREG- Hold Following HIORD-
tHREG
0-
-
ns
HWAIT- Delay Falling from HIORD-
tDFWT
-
-
35
ns
HWAIT- Width Time
tWWT
-
-
12,000
ns
HIOWR- High from HWAIT- High
tDRIOWR
0-
-
ns
RADIO TX DATA - TX PATH
TXC Period
tTXC
4* tTMCK
--
ns
TXC Width Hi
tCHM
31
-
-
ns
TXC Width Lo
tCLM
31
-
-
ns
RADIO RX DATA - RX PATH
RX_RDY Setup Time to RXC Positive Edge (See Note 5)
tSURX_RDY
10
-
-
ns
RX_RDY Hold Time from RXC Positive Edge (See Note 6)
tHRX_RDY
45
-
-
ns
RX_PE2 Delay from RX_RDY deAssert (See Note 10)
tDRX_PE2
-3 * tMCLK
-ns
RX_PE2 Low Pulse Width (See Note 9)
tWRX_PE2
-4 * tMCLK
-ns
RXD Setup Time to RXC Positive Edge (See Note 7)
tSURXD
10
-
-
ns
RXD Hold Time from RXC Positive Edge (See Note 7)
tHRXD
0-
-
ns
RXC Period (See Note 12)
tRXC
-3 * tMCLK
-ns
RXC Width Hi
tRCHM
31
-
-
ns
RXC Width Lo
tRCLM
31
-
-
ns
NOTES:
6. MD_RDY is and'ed with RXC_ONE_SHOT (RXDAV) to shift data in shift register. RX_RDY is not required to be valid until 1 MCLK after RXC is
sampled high. Therefore, a negative setup time could be used. Since this is an unlikely scenario, we will leave it at a nominal 10ns setup time.
7. MD_RDY is and'ed with RXC_ONE_SHOT (RXDAV) to shift data in shift register. Therefore, for the last data bit, the MD_RDY must be held
active until RXC_ONE_SHOT is sampled high by MAC's MCLK. However, it is assumed that BBP will be used in a mode that keeps RX_RDY
(MD_RDY) and RXC running until RX_PE2 is de-asserted. The MAC will stop processing data after the number of bits retrieved from the PLCP
header length field are received. Therefore, the RX_RDY hold time with respect to RXC does not matter. However, should the RX_RDY signal
be cleared when the last RXD bit is received the hold time w/r RXC must be honored.
8. RXC positive edge clocks a flop which stores the RXD for internal usage.
9. RXC period (and Hi/Lo times) must be long enough for flops clocked by MAC MCLK to see 1 RXC high and 1 RXC low.
10. RX_PE inactive width at BBP is 3 BBP CLK's. Since BBP CLK and MAC CLK can be async minimum should be 4 MAC CLKs.
11. When RX_RDY drops before expected number of RXD bits is received, then TX/RX FSM in mpctl.v signals timers which clear rx_pe2_int.
AC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
HFA3842


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